INIT TIMER Register (0x8) - INIT TIMER Register (0x8) - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)
Document ID
PG436
Release Date
2026-06-23
Version
1.0 English
The INIT register is used for lane initialization. The following table shows the register bit description. This is a common register for both C-PHY and D-PHY configuration.
Recommended: AMD recommends that you use one millisecond or longer as T_INIT for the MIPI D-PHY TX core.
Table 1. INIT Register Bit Description
Bits Name Access Type Default Value Description
31:8 Reserved RO 0x0 Reserved
7:0 init_timer   0xc4 Initialization timer value in microseconds.

Programmable Value = (Init Value in micro seconds *1000)/1024.