The MIPI TX C-PHY/D-PHY GUI does not have an I/O Assignment tab and you need to use consolidated I/O planning in the main Vivado IDE Planning that is IO planner. You can select any I/O for the clock and data lanes in the TX core configuration for the selected X5IO bank. There are several restrictions with both D-PHY and C-PHY that need to be considered when planning the pinout of a design. The following figures describe the X5IO PHY resources and are referenced to illustrate the concepts discussed in the D-PHY and C-PHY I/O planning guidelines that follow.
MIPI D-PHY TX Guidelines
In MIPI D-PHY, clock and data lanes are implemented in pin pairs, which are illustrated above as pins that share an X5PHIO_XCVR_X2 site and have a pin name that indicate that they are P and N pairs. For example IO_L0P_H0O0P1_700 and IO_L0N_H0O0N1_700 are a pair because they share the same bank an the IO_L0P and IO_L0N portion of the pin name are paired. It is important that D-PHY pins maintain the "P" and "N" in the IP name as the pin site. Swapping these pins is not allowed.
Due to shared clocking resources, interfaces within the same bank must share the same line rate. When combining multiple interfaces into the same bank, only one core must be generated to "include shared logic" to allow its X5PLL interface to be shared.
MIPI C-PHY TX Guidelines
In MIPI C-PHY, clock and data lanes are implemented in pin triplets, which are illustrated above as pins that share an Triplet Interface Group, and have fixed Line A, B, C positions. Swapping these pins is not allowed. When a C-PHY Triplet is used, PIn P3 for Interface Group A and Pin P5 for interface can only be used as TX and must bypass the PHY resources (i.e. must be driven from the fabric, not the PHY).
Due to shared clocking resources, interfaces within the same bank must share the same line rate. When combining multiple interfaces into the same bank, only one core must be generated to "include shared logic" to allow its X5PLL interface to be shared.