The MIPI TX C-PHY/D-PHY GUI does not have an I/O Assignment tab, and you need to use consolidated I/O planning in the main AMD Vivado™ IDE Planning that is IO planner. You can select any I/O for the clock and data lanes in the TX core configuration for the selected X5IO bank. There are several restrictions with both D-PHY and C-PHY that need to be considered when planning the pinout of a design. The following figures describe the X5IO PHY resources and are referenced to show the concepts discussed in the D-PHY and C-PHY I/O planning guidelines that follow.
Figure 1. X5IO Octad Layout
Figure 2. Bank Structure for X5IO PHY
