I/O Interface Signals - I/O Interface Signals - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID: PG436
Release Date: 2025-11-20
Version: 1.0 English

The following table shows the core ports that are associated with the I/O interface for C-PHY and D-PHY modes.

Table 1. TX PHY I/O Interface
Signal	Direction	Domain Clock	Description
clk_txp	Output	N/A	Positive differential serial data output pin for clock lane. Available only for D-PHY mode.
clk_txn	Output	N/A	Negative differential serial data output pin for clock lane. Available only for D-PHY mode.
data_txp[<n-1>:0]	Output	N/A	Positive differential serial data output pin for data lane(s). Available only for D-PHY mode.
data_txn[<n-1>:0]	Output	N/A	Negative differential serial data output pin for data lane(s). Available only for D-PHY mode.
tx_a [<n-1>:0]	Output	N/A	High-Speed serial data output pin. Available only for C-PHY mode.
tx_b [<n-1>:0]	Output	N/A	High-Speed serial data output pin. Available only for C-PHY mode.
tx_c [<n-1>:0]	Output	N/A	High-Speed serial data output pin. Available only for C-PHY mode.
<n> is the data lane number.