HS_TIMEOUT Register (0x10 offset) - HS_TIMEOUT Register (0x10 offset) - 1.0 English

HS_TIMEOUT Register (0x10 offset) - HS_TIMEOUT Register (0x10 offset) - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID

PG436

Release Date

2026-06-23

Version

1.0 English

The HS_TIMEOUT register is used as a watchdog timer in high-speed mode. The following table shows the HS_TIMEOUT register bit description. This is a common register for both C-PHY and D-PHY configuration.

Table 1. HS_TIMEOUT Register Bit Description
Bits	Name	Access Type	Default Value	Description
31:0	hs_timeout	R/W	0x10005 (65541)	It is the Maximum packet length. This value has to be programmed per lane. When in D-PHY Mode, the value is in Bytes and when in C-PHY mode, the value is in Symbols. Range for D-PHY: 1000–65541 (bytes) Range for C-PHY: 3500–229523 (Symbols)