HS_TIMEOUT Register (0x10 Offset) - HS_TIMEOUT Register (0x10 Offset) - 1.0 English

HS_TIMEOUT Register (0x10 Offset) - HS_TIMEOUT Register (0x10 Offset) - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID

PG436

Release Date

2025-11-20

Version

1.0 English

The HS_TIMEOUT register is used as a watchdog timer in high-speed mode. The following table shows the HS_TIMEOUT register bit description. This is a common register for both C-PHY and D-PHY configurations.

Table 1. HS_TIMEOUT Register Bit Description
Bits	Name	Default Value	Access Type	Description
31:0	hs_timeout	0x10005(65541)	R/W	Its the Maximum packet length , this value has to be programmed per lane. When in DPHY Mode, the value is in bytes and when in CPHY mode, the value is in symbols. Range for D-PHY: 1000-65541 (bytes) Range for C-PHY: 3500-229393 (Symbols)