- Compliant with MIPI Alliance Standard for D-PHY Specification version 2.5 and MIPI Alliance Standard for C-PHY Specification version 2.0.
- Synchronous transfer at high-speed mode with a bit rate of 400 to 4500 Mb/s in D-PHY mode and 400 to 4500 Msps in C -PHY mode.
- One clock lane and up to four data lanes for D-PHY configuration.
- Three data lanes for C-PHY configuration.
- Asynchronous transfer at low-power mode with a bit rate of 10 Mb/s.
- Ultra low-power mode and high-speed mode for clock lane.
- Ultra-low-power mode, high-speed mode, and escape mode for Single data lane.
- PHY-Protocol Interface (PPI) to connect CSI-2 and DSI applications.
- Optional AXI4-Lite interface for register access.