The MIPI TX C-PHY/D-PHY core can be configured as a C-PHY TX or D-PHY TX. It supports highspeed data transfer from 400 to 4500 Mb/s for D-PHY and 400 to 4500 Msps for C-PHY, and control data can be transferred using Low-Power Data Transfer mode at 10 Mb/s. The PPI interface allows a seamless interface to DSI and/or CSI IP cores.
Using the MIPI TX C-PHY/D-PHY core AMD Vivado™ Integrated Design Environment (IDE)-based I/O planner, you can customize the data lane(s) selection by selecting the I/O bank followed by the clock lane. Optionally, the MIPI TX C-PHY/D-PHY core provides an AXI4-Lite interface to update the protocol timer values and retrieve the core status for debugging purposes.