Endianness Details - Endianness Details - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID
PG436
Release Date
2025-11-20
Version
1.0 English
All registers are in little endian format, as shown in the following table.
Table 1. 32-bit Little Endian Example
Byte Address Offset Bit Boundaries
Byte 0 0x0 [7:0]
Byte 1 0x1 [15:8]
Byte 2 0x2 [23:16]
Byte 3 0x3 [31:24]
Table 2. MIPI TX C-PHY/D-PHY Core Register Space
Offset C-PHY TX D-PHY TX
0x0 CONTROL CONTROL
0x4 Reserved Reserved
0x8 INIT TIMER INIT TIMER
0xC Reserved Reserved
0x10 HS_TIMEOUT HS_TIMEOUT
0x14 ESC_TIMEOUT ESC_TIMEOUT
0x18 Reserved CL_STATUS
0x1C DL0_STATUS DL0_STATUS
0x20 DL1_STATUS DL1_STATUS
0x24 DL2_STATUS DL2_STATUS
0x28 Reserved DL3_STATUS
0x2C Reserved Reserved
0x30 Reserved Reserved
0x34 Reserved Reserved
0x38 PROG_SEQ_CTRL Reserved
0x3C PROG_SEQ_DATA0 Reserved
0x40 PROG_SEQ_DATA1 Reserved