The DL_STATUS register is the same for
data lanes 0, 1, 2, and 3. This register provides data lane status and state machine
control. The following table provides the DL_STATUS register bit description. DL_STATUS
register for data lanes 0,1 and 2 are common for both C-PHY and D-PHY configurations.
DL_STATUS register for data lane 3 is only for D-PHY.
| Bits | Name | Default Value | Access type | Description |
|---|---|---|---|---|
| [31:16] | dl0_pkt_cnt | 0x0 | RO | Number of packets received or transmitted on the data lane. This field is updated using the txwordclkhs clock and the TX clock lane must be in high-speed mode when reset is applied to the PHY TX IP. Otherwise, this value does not get reset for MIPI PHY TX IP configuration. |
| [6] | dl0_stopstate | 0x0 | RO | Data lane is in the Stop state. |
| [5] | dl0_esc_abort | 0x0 | R/W1C | This bit is set after the Data Lane Escape Timeout (Escape Mode Timeout.) Write-to-1 clears this bit. |
| [4] | dl0_hs_abort | 0x0 | R/W1C | Set after the Data Lane High-Speed Timeout (HS_TIMEOUT) has elapsed. Write to 1 clears this bit. |
| [3] | dl0_init_done | 0x0 | RO | Set after the lane has completed initialization. |
| [2] | dl0_ulps | 0x0 | RO | Set to 1 when the core is in ULPS mode. |
| [1:0] | dl0_mode | 0x0 | RO |
|