Required Constraints
This section defines the additional constraint requirements for the core. Constraints are provided with a Design Constraints (XDC) file. An XDC is provided with the HDL example design to give a starting point for constraints for your design.
Device, Package, and Speed Grade Selections
Select the device, package, and speed grades after referring to the following data sheets for details on supported maximum data rate supported.
- Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
Clock Frequencies
Specify core_clk as follows:
create_clock -name core_clk -period 5.000 [get_ports core_clk]This constraint defines the frequency of core_clk that is supplied to the MMCM and PCS logic.
Clock Management
The MIPI TX C-PHY/D-PHY core uses an MMCM to generate the general interconnect clocks, and the PLL is used to generate the serial clock and parallel clocks for the PHY. The input to the MMCM is constrained as shown in Clock Frequencies. No additional constraints are required for the clock management.
Clock Placement
This section is not applicable for this IP core.
Banking
The clock lane and data lane(s) are implemented on the MIPI dedicated pins.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
MIPI standard serial I/O ports need to use MIPI TX C-PHY/D-PHY for the I/O standard in the XDC file for AMD Versal™ and AMD Versal™ Gen 2 device families. The LOC and I/O standards must be specified in the XDC file for all input and output ports of the design. MIPI TX C-PHY/D-PHY generates the IO pin LOC for the pins that are selected during IP customization.