The MIPI TX C-PHY/D-PHY Controller requires a 200 MHz free
running clock
(core_clk). This clock is used as input to the
Mixed-Mode Clock Manager (MMCM), and the required clocks are generated based on IP
configurations.Note:
core_clk should be either coming from the on-board oscillator or the single
MMCM or the PLL from target FPGA device. core_clk should
not be generated from the cascaded MMCM blocks.The following
figures show the MIPI TX PHY clock diagrams. The MIPI TX C-PHY/D-PHY core takes core_clk as an input and generates the necessary
clocks from the MMCM.
Figure 1. MIPI D-PHY TX Clocking
Figure 2. MIPI C-PHY TX Clocking
The following table provides details about the core clocks.
| Clock | Frequency | IP Configuration | Notes |
|---|---|---|---|
| core_clk | 200.000 MHz | All | Used for control logic and input to MMCM. |
| txwordclkhs_out | 25.000 – 281.25 MHz Derived from the line rate divided by 16 | Include Shared Logic in core | Input to PHY and used to transmit high-speed data. |
| clkoutphy_out | Line rate | Include Shared Logic in core | PHY serial clock. |
| txclkesc_out | 10.000–20.000 MHz | Include Shared Logic in core | Clock used for Escape mode operations |
| clkoutphy_90_out | Line rate | Include Shared Logic in core | 90-degree phase shift of clkoutphy_out clock |
| txclkesc_in | 10.000–20.000 MHz | Include Shared Logic in example design |
Clock used for Escape mode operations |
| txwordclkhs_in | 25.000 – 281.25 MHz D-PHY: Derived from the line rate divided by 16 C-PHY: Derived from line rate divided by 7 for line rates from 400 to 2250 and divided by 14 for line rates from 2251 to 4500 | Include Shared Logic in example design | High-speed mode clock |
| clkoutphy_in | Line rate | Include Shared Logic in example design | PHY serial clock |
| clkoutphy_90_in | Line rate | Include Shared Logic in example design | 90-degree phase shift of clkoutphy_in clock |
| pll_clkout0_out | 25.000 – 281.25 MHz Derived from the line rate divided by 16 | Include Shared Logic in core and C-PHY mode | High-speed mode clock |
| shared_pll_clkout0_in | 25.000 – 281.25 MHz Derived from the line rate divided by 16 | Include Shared Logic in example design and C-PHY mode | High-speed mode clock |
Important: All the input clocks supplied to
the MIPI TX C-PHY/D-PHY should have ±100 PPM difference and violating this results in
either data corruption or data duplication.