Included in the example design
sources are circuits for clock and reset management. The following table shows the ports
on the core that are associated with system clock and reset.
| Signal | Direction | Clock Domain | Description |
|---|---|---|---|
| core_clk | I | N/A | A stable core clock used for control logic. |
| core_rst | I | core_clk | An active-High reset signal. |
| system_rst_out | O | core_clk | An active-High system reset output to be used by the example design level logic. This port is available when Shared Logic is in the Core is selected. |
| mmcm_lock_out | O | Async | MMCM lock indication. This port is not available when shared logic in the core is selected in D-PHY TX Configuration. |
| pll_lock_out | O | Async | PLL lock indication in shared logic is in core configuration. |
| init_done | O | core_clk | An active-High signal that indicates lane initialization is done. |
| pll_lock_in | I | Async | PLL lock indication from Master MIPI TX PHY core. |
| iophy_intf_rdy | O | Async | Indication of IO PHY reset sequence completion |
| clkoutphy_90_out | O | PLL Clock | 90 Phase shifted PLL Clock |
| clkoutphy_out | O | PLL CLock | Clock out PHY for PHY |
| txwordclkhs_out | O | PPI clock | PPI clock for the PPI Interface |
| clkoutphy_90_in | I | PLL clock | 90 Phase shifted PLL Clock |
| clkoutphy_in | I | PLL Clock | Clock out PHY for PHY |
| txwordclkhs_in | I | PPI clock | PPI clock for the PPI Interface |