The following figure shows the sharable resource connections from the MIPI TX CPHY/DPHY core with shared logic included (MIPI_DPHY_PRIMARY) to the instance of another MIPI TX CPHY/DPHY core without shared logic (MIPI_DPHY_SECONDARY). Both cores are configured with DPHY mode.
Figure 1. Shared Logic Example of MIPI TX CPHY/DPHY Core for DPHY
