CONTROL Register (0x0) - CONTROL Register (0x0) - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)
Document ID
PG436
Release Date
2025-11-20
Version
1.0 English
The following table shows the CONTROL register bit mapping and description. This is a common register for both C-PHY and D-PHY configuration.
Table 1. CONTROL Register Bit Description
Bits Name Access Type Default Value Description
[31] Reserved RO 0x0 Reserved.
[30] phy_mode RO 0x0 PHY mode
  • 1: D-PHY controller mode
  • 0: C-PHY controller mode
[29:2] Reserved RO 0x0 Reserved
[1] phy_en R/W 0x1 Enable bit for PHY.
  • 1: PHY controller is enabled.
  • 0: PHY controller is disabled
[0] phy_srst R/W 0x0

Soft reset for PHY Controller.

If 1 is written to this bit, the PHY controller fabric logic and status registers are reset.