CL_STATUS Register (0x18) - CL_STATUS Register (0x18) - 1.0 English

CL_STATUS Register (0x18) - CL_STATUS Register (0x18) - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID

PG436

Release Date

2025-11-20

Version

1.0 English

CL_STATUS register provides clock lane status and state machine control. The following table provides CL_STATUS register bit description. This register is used in D-PHY configuration only.

Table 1. CL_STATUS Register Bit Description
Bits	Name	Default Value	Access Type	Description
[31:5]	Reserved	0x0	RO	Reserved
[4]	cl_stopstate	0x0	RO	Clock lane is in the Stop state.
[3]	cl_init_done	0x0	RO	Set after the lane has completed initialization.
[2]	cl_ulps	0x0	RO	Set to 1 when the core in ULPS (ULP State) mode.
[1:0]	cl_mode	0x0	RO	2’b00: Low Power Mode (Control Mode) 2’b01: High Speed Mode 2’b10: Escape Mode