AXI4-Lite Interface - AXI4-Lite Interface - 1.0 English - PG436

MIPI TX C-PHY/D-PHY LogiCORE IP Product Guide (PG436)

Document ID
PG436
Release Date
2025-11-20
Version
1.0 English

The register interface uses an AXI4-Lite interface, which was selected because of its simplicity. The following figures show typical AXI4-Lite write and read transaction timings.

Figure 1. AXI4-Lite Write Timing Diagram
Figure 2. AXI4-Lite Read Timing Diagram