XMPU - XMPU - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English

The ISP Tile integrates an Xilinx Memory Protection Unit (XMPU) with the NoC NSU path, ensuring control over access permissions to internal ISP Tile programming registers.