User Parameters List - User Parameters List - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)
Document ID
PG432
Release Date
2025-11-20
Version
2.0 English
The following table details the user parameters. This list is subject to change in terms of names and number of parameters.
Table 1. User Parameters List
User Parameter Name Display Name Default Value Range Description
C_TILE<0/1/2>_ENABLE Enable TILE<0/1/2> TRUE TRUE/FALSE By default, Tile0 is enabled. By default, Tile1 and Tile2 are disabled.
C_TILE<0/1/2>_CONFIG Configuration 0 0 - 1 By default, the Tile<0/1/2> is in Basic mode. Set this parameter to 1 to change to Advanced mode.
C_TILE<0/1/2>_ISP0_IO_TYPE ISP0 IO Type 1 0 - 3 The Tile<0/1/2> ISP0 core I/O type can be set to LILO, LIMO, and MIMO by setting this parameter as 1, 2, and 3, respectively. When Tile<0/1/2> is disabled, this parameter is updated to 0.
C_TILE<0/1/2>_ISP1_IO_TYPE ISP1 IO Type 1 0 - 3 The Tile<0/1/2> ISP1 core I/O type can be set to LILO, LIMO, and MIMO by setting this parameter as 1, 2, and 3, respectively. When Tile<0/1/2> is disabled, this parameter is updated to 0.
C_TILE<0/1/2>_ISP0_LIVE_INPUTS ISP0 Live inputs 1 0 - 4 Determines the number of live inputs to the Tile<0/1/2> ISP0 core.
C_TILE<0/1/2>_ISP1_LIVE_INPUTS ISP1 Live inputs   0 - 2 Determines the number of live inputs to the Tile<0/1/2> ISP1 core.
C_TILE<0/1/2>_ISP0_MEM_INPUTS ISP0 Memory inputs 0 0 - 1 Determines the number of memory inputs to the Tile<0/1/2> ISP0 core.
C_TILE<0/1/2>_ISP1_MEM_INPUTS ISP1 Memory inputs 0 0 - 1 Determines the number of memory inputs to the Tile<0/1/2> ISP1 core.
C_TILE<0/1/2>_ISP0_RPU RPU 6 6 - 9 Determines the Tile<0/1/2> ISP0 core RPU mapping.
  • RPU6: 6
  • RPU7: 7
  • RPU8: 8
  • RPU9: 9
C_TILE<0/1/2>_ISP1_RPU RPU 6 6 - 9 Determines the Tile<0/1/2> ISP1 core RPU mapping.
  • RPU6: 6
  • RPU7: 7
  • RPU8: 8
  • RPU9: 9
C_TILE<0/1/2>_ISP0_IIC_SELECT IIC 8 0 - 9 Determines the Tile<0/1/2> ISP0 core IIC from the PS or PL.
  • PS_I3C_I2C0: 0
  • PS_I3C_I2C1: 1
  • PS_I3C_I2C2: 2
  • PS_I3C_I2C3: 3
  • PS_I3C_I2C4: 4
  • PS_I3C_I2C5: 5
  • PS_I3C_I2C6: 6
  • PS_I3C_I2C7: 7
  • PL: 8
  • Disable: 9

When Tile<0/1/2> is disabled, this parameter is updated to 9.
C_TILE<0/1/2>_ISP0_IIC_PS_CHECK This IIC is required to be manually enabled in the peripherals section of PS Wizard FALSE TRUE/FALSE When the Tile<0/1/2> ISP0 core IIC to be from PS, this parameter must be set to TRUE.
C_TILE<0/1/2>_ISP1_IIC_SELECT IIC 8 0 - 9 Determines the Tile<0/1/2> ISP1 core IIC from the PS or PL.
  • PS_I3C_I2C0: 0
  • PS_I3C_I2C1: 1
  • PS_I3C_I2C2: 2
  • PS_I3C_I2C3: 3
  • PS_I3C_I2C4: 4
  • PS_I3C_I2C5: 5
  • PS_I3C_I2C6: 6
  • PS_I3C_I2C7: 7
  • PL: 8
  • Disable: 9

When Tile<0/1/2> is disabled, this parameter is updated to 9.
C_TILE<0/1/2>_ISP1_IIC_PS_CHECK This IIC is required to be manually enabled in the peripherals section of PS Wizard FALSE TRUE/FALSE When the Tile<0/1/2> ISP1 Core IIC is from the PS, this parameter must be set to TRUE.
C_TILE<0/1/2>_ISP0_IIC_PL_FREQ IIC Frequency (in kHz) 100 1.0 to 1000.0 Determines the approximate frequency of the master mode generated SCL clock signal (Hz) of the Tile<0/1/2> ISP0 Core.
C_TILE<0/1/2>_ISP1_IIC_PL_FREQ IIC Frequency (in kHz) 100 1.0 to 1000.0 Determines the approximate frequency of the master mode generated SCL clock signal (Hz) of the Tile<0/1/2> ISP1 Core.
C_TILE<0/1/2>_ISP0_IIC_PL_ADDR Address mode 7 bit 7 bit/10 bit Enables or disables the 10-bit addressing mode of the Tile<0/1/2> ISP0 Core. Logic resource savings result when 10-bit addressing is disabled.
C_TILE<0/1/2>_ISP1_IIC_PL_ADDR Address mode 7 bit 7 bit/10 bit Enables or disables the 10-bit addressing mode of the Tile<0/1/2> ISP1 Core. Logic resource savings result when 10-bit addressing is disabled.
C_TILE<0/1/2>_ISP0_GPIO_SELECT GPIO 3 0 - 3 Determines the Tile<0/1/2> ISP0 Core GPIO from the PS or PL.
  • PSX_GPIO0: 0
  • PSX_GPIO1: 1
  • PL: 2
  • Disable: 3

When Tile<0/1/2> is disabled, this parameter is updated to 3.
C_TILE<0/1/2>_ISP0_GPIO_PS_CHECK This GPIO is required to be manually enabled in the peripherals section of PS Wizard. FALSE TRUE/FALSE When the Tile<0/1/2> ISP0 Core GPIO is from the PS, this parameter must be set to TRUE.
C_TILE<0/1/2>_ISP1_GPIO_SELECT GPIO 0 0/1 Determines the Tile<0/1/2> ISP1 Core GPIO from the PS or PL.
  • PSX_GPIO0: 0
  • PSX_GPIO1: 1
  • PL: 2
  • Disable: 3

When Tile<0/1/2> is disabled, this parameter is updated to 3.
C_TILE<0/1/2>_ISP1_GPIO_PS_CHECK This GPIO is required to be manually enabled in the peripherals section of PS Wizard. FALSE TRUE/FALSE When the Tile<0/1/2> ISP1 Core GPIO is from the PS, this parameter must be set to TRUE.
C_TILE<0/1/2>_ISP0_GPIO_PL_WIDTH GPIO Width 32 1 - 32 Determines the GPIO width for the Tile<0/1/2> ISP0 Core.
C_TILE0_ISP0_GPIO_PL_ALL_INPUTS All Inputs GPIO 0 0 - 1 By default, the Tile<0/1/2> ISP0 core GPIO has general purpose input pins, output pins, and 3-state pins. To have all pins as inputs, set this parameter to 1.
C_TILE0_ISP0_GPIO_PL_ALL_OUTPUTS All Outputs GPIO 0 0 - 1 By default, the Tile<0/1/2> ISP0 core GPIO has general purpose input pins, output pins, and 3-state pins. To have all pins as outputs, set this parameter to 1.
C_TILE<0/1/2>_ISP1_GPIO_PL_WIDTH GPIO Width 32 1 - 32 Determines the GPIO width for the Tile<0/1/2> ISP1 Core.
C_TILE0_ISP1_GPIO_PL_ALL_INPUTS All Inputs GPIO 0 0 - 1 By default, the Tile<0/1/2> ISP1 core GPIO has general purpose input pins, output pins, and 3-state pins. To have all pins as inputs, set this parameter to 1.
C_TILE0_ISP1_GPIO_PL_ALL_OUTPUTS All Outputs GPIO 0 0 - 1 By default, the Tile<0/1/2> ISP1 core GPIO has general purpose input pins, output pins, and 3-state pins. To have all pins as outputs, set this parameter to 1.
C_TILE<0/1/2>_ISP0_CORE_CLK Core Clock (MHz) 600 1 - 800  
C_TILE<0/1/2>_ISP1_CORE_CLK Core Clock (MHz) 600 1 - 800  
C_TILE<0/1/2>_ISP0_BASIC_DATA_FORMAT Common Pixel Format 16 8, 10, 12, 14, 16 In Basic mode, this parameter sets the data format of the IBA's corresponding to the Tile<0/1/2> ISP0 core.
  • RAW8: 8
  • RAW10: 10
  • RAW12: 12
  • RAW14: 14
  • RAW16: 16
C_TILE<0/1/2>_ISP0_BASIC_PPC Pixels per clock 4 1, 2, 4 In Basic mode, this parameter sets the pixels per clock of the IBA's corresponding to the Tile<0/1/2> ISP0 core.
C_TILE<0/1/2>_ISP0_IBA<0/1/2/3*>_RES_HOR Max Horizontal Resolution 3840 720, 1280, 1920, 2048, 3840, 4096 Determines the maximum horizontal resolution of the Tile<0/1/2> ISP0 Core IBA<0/1/2/3*>.
C_TILE<0/1/2>_ISP0_IBA<0/1/2/3*>_RES_VER Max Vertical Resolution 2160 480, 720, 1080, 1536, 2160, 3072, 4096 Determines the maximum vertical resolution of the Tile<0/1/2> ISP0 Core IBA<0/1/2/3*>.
C_TILE<0/1/2>_ISP0_IBA<0/1/2/3*>_FPS FPS

60 for C_TILE<0/1/2>_ISP0_IBA0_FPS

0 for C_TILE<0/1/2>_ISP0_IBA<1/2/3*>_FPS

 0, 10, 15, 20, 25, 30, 35, 40, 45, 50, 60 Determines the FPS of the Tile<0/1/2> ISP0 Core IBA<0/1/2/3*>.
C_TILE<0/1/2>_ISP0_IBA<0/1/2/3*>_DATA_FORMAT Pixel Format 16 8, 10, 12, 14, 16 Determines the data format of the Tile<0/1/2> ISP0 Core IBA<0/1/2/3*>.
C_TILE<0/1/2>_ISP0_IBA<0/1/2/3*>_PPC Pixels Per Clock 4 1, 2, 4 Determines the pixels per clock of the Tile<0/1/2> ISP0 Core IBA<0/1/2/3*>.
C_TILE<0/1/2>_ISP0_IBA<0/1/2/3*>_VCID Virtual Channel 0 0 - 3 Determines the virtual channel ID of the Tile<0/1/2> ISP0 Core IBA<0/1/2/3*>.
C_TILE<0/1/2>_ISP1_BASIC_DATA_FORMAT Common Pixel Format 16 8, 10, 12, 14, 16 In Basic mode, this parameter sets the data format of the IBA's corresponding to the Tile<0/1/2> ISP0 core.
  • RAW8: 8
  • RAW10: 10
  • RAW12: 12
  • RAW14: 14
  • RAW16: 16
C_TILE<0/1/2>_ISP1_BASIC_PPC Pixels per clock 4 1, 2, 4 In Basic mode, this parameter sets the pixels per clock of the IBA's corresponding to the Tile<0/1/2> ISP1 core.
C_TILE<0/1/2>_ISP1_IBA<3*/4>_RES_HOR Max Horizontal Resolution 3840 720, 1280, 1920, 2048, 3840, 4096 Determines the maximum horizontal resolution of the Tile<0/1/2> ISP1 Core IBA<3*/4>.
C_TILE<0/1/2>_ISP1_IBA<3*/4>_RES_VER Max Vertical Resolution 2160 480, 720, 1080, 1536, 2160, 3072, 4096 Determines the maximum vertical resolution of the Tile<0/1/2> ISP1 Core IBA<3*/4>.
C_TILE<0/1/2>_ISP1_IBA<3*/4>_FPS FPS 60 for C_TILE<0/1/2>_ISP1_IBA4_FPS

00 for C_TILE<0/1/2>_ISP1_IBA3*_FPS

 0, 10, 15, 20, 25, 30, 35, 40, 45, 50, 60 Determines the FPS of the Tile<0/1/2> ISP1 Core IBA<3*/4>.
C_TILE<0/1/2>_ISP1_IBA<3*/4>_DATA_FORMAT Pixel Format 16 8, 10, 12, 14, 16 Determines the data format of the Tile<0/1/2> ISP1 Core IBA<3*/4>.
C_TILE<0/1/2>_ISP1_IBA<3*/4>_PPC Pixels Per Clock 4 1,2,4 Determines the pixels per clock of Tile<0/1/2> ISP1 Core IBA<3*/4>.
C_TILE<0/1/2>_ISP1_IBA<3*/4>_VCID Virtual Channel 0 0 - 3 Determines the virtual channel ID of the Tile<0/1/2> ISP1 Core IBA<3*/4>.
C_TILE<0/1/2>_ISP<0/1>_ENABLE_MP Enable Primary Output TRUE TRUE/FALSE By default, the Tile<0/1/2> ISP0 core primary output is enabled. To disable primary ouptu, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_ENABLE_SP Enable Secondary Output FALSE TRUE/FALSE By default, the Tile<0/1/2> ISP0 core secondary output is disabled. To enable the secondary output, set this parameter to TRUE.
C_TILE<0/1/2>_ISP0_OBA0_PPC Pixels Per Clock 4 1, 2, 4 Determines the Tile<0/1/2> ISP0 core PO and SO OBA pixels per clock. Pixels per clock to be streamed out on the PO and SO of ISP0 core.
C_TILE<0/1/2>_ISP0_OBA0_MP_RGB888 RGB888 TRUE TRUE/FALSE By default,the RGB888 data format is included in the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP0 core. To exlclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_MP_YUV422 YUV422 TRUE TRUE/FALSE By default, the YUV422 data format is included in the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP0 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_MP_YUV420 YUV420 FALSE TRUE/FALSE By default, the YUV420 data format is excluded from the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP0 core. To include it in the list, set this parameter to TRUE.
C_TILE<0/1/2>_ISP0_OBA0_MP_Y Y TRUE TRUE/FALSE By default, the Y-only data format is included in the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP0 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_MP_BPP Bits Per Component 10 8, 10 Determines the Tile<0/1/2> ISP0 core primary output OBA pixels per clock.
C_TILE<0/1/2>_ISP0_OBA0_SP_RGB888 RGB888 TRUE TRUE/FALSE By default, the RGB888 data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP0. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_SP_YUV422 YUV422 TRUE TRUE/FALSE By default, the YUV422 data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP0. To exclude if from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_SP_YUV420 YUV420 FALSE TRUE/FALSE By default, the YUV420 data format is excluded from the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP0 core. To include it in the list, set this parameter to TRUE.
C_TILE<0/1/2>_ISP0_OBA0_SP_Y Y TRUE TRUE/FALSE By default, the Y-only data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP0 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_SP_IR Monochrome (IR) TRUE TRUE/FALSE By default, the monochrome (IR) data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP0 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP0_OBA0_SP_BPP Bits Per Component 10 8, 10 Determines the Tile<0/1/2> ISP0 core secondary output OBA pixels per clock.
C_TILE<0/1/2>_ISP1_ENABLE_MP Enable Primary Output TRUE TRUE/FALSE By default, the Tile<0/1/2> ISP1 core primary output is enabled. To disable the primary output, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_ENABLE_SP Enable Secondary Output FALSE TRUE/FALSE By default, the Tile<0/1/2> ISP1 core secondary output is disabled. To enable the secondary output, set this parameter to TRUE.
C_TILE<0/1/2>_ISP1_OBA1_PPC Pixels Per Clock 4 1, 2, 4 Determines the Tile<0/1/2> ISP1 core PO and SO OBA pixels per clock. Pixels per clock to be streamed out on PO and SO of the ISP1 core.
C_TILE<0/1/2>_ISP1_OBA1_MP_RGB888 RGB888 TRUE TRUE/FALSE By default, the RGB888 data format is included in the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP1 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_MP_YUV422 YUV422 TRUE TRUE/FALSE By default, the YUV422 data format is included in the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP1 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_MP_YUV420 YUV420 FALSE TRUE/FALSE By default, the YUV420 data format is excluded from the list of supported data formats on the primary output (PO) OBA of the Tile<0/1/2> ISP1 core. To include it in the list, set this parameter to TRUE.
C_TILE<0/1/2>_ISP1_OBA1_MP_Y Y TRUE TRUE/FALSE By default, the Y-only data format is included in the list of supported data format on the primary output (PO) OBA of the Tile<0/1/2> ISP1 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_MP_BPP Bits Per Component 10 8, 10 Determines the Tile<0/1/2> ISP1 core primary output OBA pixels per clock.
C_TILE<0/1/2>_ISP1_OBA1_SP_RGB888 RGB888 TRUE TRUE/FALSE By default, the RGB888 data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP1 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_SP_YUV422 YUV422 TRUE TRUE/FALSE By default, the YUV422 data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP1 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_SP_YUV420 YUV420 FALSE TRUE/FALSE By default, the YUV420 data format is excluded from the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP1 core. To include it in the list, set this parameter to TRUE.
C_TILE<0/1/2>_ISP1_OBA1_SP_Y Y TRUE TRUE/FALSE By default, the Y-only data format is included in the list of supported data formats on the secondary output (SO) OBA of Tile<0/1/2>. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_SP_IR Monochrome (IR) TRUE TRUE/FALSE By default, the monochrome (IR) data format is included in the list of supported data formats on the secondary output (SO) OBA of the Tile<0/1/2> ISP1 core. To exclude it from the list, set this parameter to FALSE.
C_TILE<0/1/2>_ISP1_OBA1_SP_BPP Bits Per Component 10 8, 10 Determines the Tile<0/1/2> ISP1 core secondary output OBA pixels per clock.
C_LLPATH<0/1>_TILE TILE 3 0 - 3 Tile selected for Path<0/1>.
  • TILE0: 0
  • TILE1: 1
  • TILE2: 2
  • None: 3
C_LLPATH<0/1>_IBA Stream input 0 0 - 4 Input stream selected for Path<0/1>.
C_LLPATH<0/1>_OBA Output 0 0 - 1 Output stream selected for Path<0/1>.
  • Primary_Output: 0
  • Secondary_Output: 1
C_LLPATH<0/1>_DELAY Delay (ns) 278 278 - 2000 Determines the low latency path<0/1> delay.
C_LLPATH<0/1>_CLK - 150 1 - 400  
C_SPEEDGRADE - -3hp   Speed grade of the part.
C_PPC_CONVERTER_ENABLE Enable 8-to-4 PPC Converter FALSE TRUE/FALSE Enable 8 to 4 PPC Converter Block.
C_PPC_CONVERTER_NUM_STREAMS Num of 4k60 streams/VCIDs 0 0, 2, 3, 4 Specifies the number of output streams supported by Converter Module.
C_PPC_CONVERTER_S0_ISP ISP instance for Stream0 0 0-6 Indicates which Tile and ISP instance the current stream is mapped to.
  • None: 0
  • TILE0 ISP0: 1
  • TILE0 ISP1: 2
  • TILE1 ISP0: 3
  • TILE1 ISP1: 4
  • TILE2 ISP0: 5
  • TILE2 ISP1: 6
C_PPC_CONVERTER_S1_ISP ISP instance for Stream1 0 0-6 Indicates which Tile and ISP instance the current stream is mapped to.
  • None: 0
  • TILE0 ISP0: 1
  • TILE0 ISP1: 2
  • TILE1 ISP0: 3
  • TILE1 ISP1: 4
  • TILE2 ISP0: 5
  • TILE2 ISP1: 6
C_PPC_CONVERTER_S2_ISP ISP instance for Stream2 0 0-6 Indicates which Tile and ISP instance the current stream is mapped to.
  • None: 0
  • TILE0 ISP0: 1
  • TILE0 ISP1: 2
  • TILE1 ISP0: 3
  • TILE1 ISP1: 4
  • TILE2 ISP0: 5
  • TILE2 ISP1: 6
C_PPC_CONVERTER_S3_ISP ISP instance for Stream3 0 0 - 6 Indicates which Tile and ISP instance the current stream is mapped to.
  • None: 0
  • TILE0 ISP0: 1
  • TILE0 ISP1: 2
  • TILE1 ISP0: 3
  • TILE1 ISP1: 4
  • TILE2 ISP0: 5
  • TILE2 ISP1: 6
C_TARGET_BOARD Target Board VEK385 VEK385 Board Target
C_FMC_MODEL FMC Model Xylon FMC GMSL2 Module Xylon FMC GMSL2 Module FMC Model
C_DESIGN_TOPOLOGY Design Topology 0 0 - 2
  • LILO MIPI Camera to HDMI Display: 0
  • LIMO MIPI Camera to HDMI Display: 1
  • MIMO DDR to DDR: 2
  1. Use the C_TILE<0/1/2>_ISP0_IBA3_* parameter when the number of streaming inputs to the TILE<0/1/2> ISP0 core is 4.
  2. Use the C_TILE<0/1/2>_ISP1_IBA3_* parameter when the number of streaming inputs to the TILE<0/1/2> ISP1 core is 2.
  3. <0/1/2> can be 0, 1, or 2.
  4. <0/1> can be 0 or 1.
  5. <0/1/2/3/4> can be 0, 1, 2, 3, or 4.