Support for VCU2 Low Latency Configuration Options - Support for VCU2 Low Latency Configuration Options - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English

Enabling low latency paths enables the end of frame (EOF) and end of line (EOL) signals for any two of the active paths across all three tiles.

Figure 1. Generate SB Signals for VCU2 Low Latency Configuration Options
Generated by Your Tool
Path <0/1>
TILE
By default, no tiles are selected for a low latency path. Select TILE0, TILE1, or TILE2 for the intended low-latency path.
Stream input
Select the IBA from the selected tile. Tile selection follows the number of inputs you chose on the Initial Configuration Options tab.
Output
Select the primary or secondary OBA output for the low-latency path.
Delay (ns)
Indicates that the generated EOL/EOF is driven out with a delay dependent on ensuring stable data is written in the DDR memory.

Enabling the sideband signals for VCU2 adds embedded logic at the ISP output. This logic uses the streaming output from the ISP (AXI4-Stream signals) to generate the additional EOF/EOL that the VCU2 IP uses to implement its low latency feature in scenarios where a ISP-DDR-VCU2 pipeline is implemented.

Figure 2. EOF EOL Logic Implementation