Soft Reset Control Register (0x04) - Soft Reset Control Register (0x04) - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID: PG432
Release Date: 2025-11-20
Version: 2.0 English

The soft reset control register resets Tile0, Tile1, and Tile2.

Table 1. Soft Reset Control Register (0x04)
Bits	Name	Reset Value	Access	Description
31:3	Reserved	N/A	N/A	Reserved
2	Tile2 soft reset	0x1	R/W	1: Tile2 is out of soft reset 0: Tile2 is under soft reset After eight clock cycles (s_axi_lite_aclk), Tile2 comes out of soft reset and this bit becomes 0x1. To bring Tile2 out of soft reset before eight clock cycles, write 0x1 to this bit.
1	Tile1 soft reset	0x1	R/W	1: Tile1 is out of soft reset 0: Tile1 is under soft reset After eight clock cycles (s_axi_lite_aclk), Tile1 comes out of soft reset and this bit becomes 0x1. To bring Tile1 out of soft reset before eight clock cycles, write 0x1 to this bit.
0	Tile0 soft reset	0x1	R/W	1: Tile0 is out of soft reset 0: Tile0 is under soft reset After eight clock cycles (s_axi_lite_aclk), Tile0 comes out of soft reset and this bit becomes 0x1. To bring Tile0 out of soft reset before eight clock cycles, write 0x1 to this bit.