Revision History - Revision History - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English

The following table shows the revision history for this document.

Section Revision Summary
11/20/2025 Version 2.0
Configuration Options Updated tab description.
Initial Configuration Options Added section.
Resources Tab Updated figure.
Inputs Tab Added new option descriptions and updated figure.
Outputs Tab Updated figure.
Support for VCU2 Low Latency Configuration Options Added new option descriptions and updated figure.
Application Example Design Configuration Options Added section.
User Parameters List Added new parameters.
Interfaces and Ports Added the MIPI_8PPC_VIDIN interface.
Clocking, Reset, Interrupt, EOL, and EOF Ports Added signals related to the MIPI_8PPC_VIDIN interface.
Register Space Updated register description.
Version Control Register (0x00) Updated register description and table values.
Implementing the Example Design Added details for Application Example Design Configuration options and updated screenshots.
08/14/2025 Version 1.0
RPU Firmware Updated topic.
05/29/2025 Version 1.0
Initial release. N/A