The S_AXI_LITE interface allows you to access the ISP version/soft reset registers, as well as, configure the PL IIC/GPIO instances, if enabled.
Refer to the following register space details of the IIC/GPIO instances.
- IIC
- AXI IIC Bus Interface LogiCORE IP Product Guide (PG090)
- GPIO
- AXI GPIO LogiCORE IP Product Guide (PG144)
The address to access each register equals the base address of S_AXI_LITE from design plus the address offset.
Note: If different tiles are enabled in different IP instances,
the base address for each tile depends on the S_AXI_LITE address of the ISP instance
in which it is enabled, but the register offset remains the same.
| Slave Segment | Offset Address Start | Offset Address End | Range |
|---|---|---|---|
| ISP Version/Reset registers | 0x0000 | 0x0FFF | 4k |
| TILE0_ISP0_IIC | 0x1000 | 0x1FFF | 4k |
| TILE0_ISP0_GPIO | 0x2000 | 0x2FFF | 4k |
| TILE0_ISP1_IIC | 0x3000 | 0x3FFF | 4k |
| TILE0_ISP1_GPIO | 0x4000 | 0x4FFF | 4k |
| TILE1_ISP0_IIC | 0x5000 | 0x5FFF | 4k |
| TILE1_ISP0_GPIO | 0x6000 | 0x6FFF | 4k |
| TILE1_ISP1_IIC | 0x7000 | 0x7FFF | 4k |
| TILE1_ISP1_GPIO | 0x8000 | 0x8FFF | 4k |
| TILE2_ISP0_IIC | 0x9000 | 0x9FFF | 4k |
| TILE2_ISP0_GPIO | 0xA000 | 0xAFFF | 4k |
| TILE2_ISP1_IIC | 0xB000 | 0xBFFF | 4k |
| TILE2_ISP1_GPIO | 0xC000 | 0xCFFF | 4k |