RGB888/YUV444 10-bit Interleaved with YUV Align - RGB888/YUV444 10-bit Interleaved with YUV Align - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)
Document ID
PG432
Release Date
2025-11-20
Version
2.0 English
Figure 1. RGB888/YUV444 10-bit Interleaved with YUV Align

The padded data is taken from the following register:

Table 1. MI_ARGB_PADDING Register
Register Name Address Width Type Reset Value Description
MI_ARGB_PADDING 0XE8501750 32 RW 0x00000000 The padding data for ARGB 8-8-8-8 format, and use bit[1:0] when 10-bit ARGB is 10-10-10-2.
Table 2. Register MI_ARGB_PADDING Bit Field Details
Field Name Bits Type Reset Value Description
argb_padding 7:0 RW 0x0 The padding data for ARGB 8-8-8-8 format, and use bit[1:0] when 10-bit ARGB is 10-10-10-2.

YUV align can be enabled using the field mp_wr_yuv_aligned of the MI_MP_FMT (Offset - 0x1314) register of the ISP IP.

The placement of components can be changed by the following fields of MI_MP_FMT(0x1314) register:

Table 3. MI_MP_FMT(0x1314) Component Details
Field Name Bits Type Reset Value Description
mp_wr_yuv_nvy 14:13 RW 0x0
  • 00: Put Y first => YC1C2
  • 01: Put Y second => C1YC2
  • 10: Put Y Third => C1C2Y
mp_wr_yuv_nv21 12 RW 0x0
  • 0: Put U before V
  • 1: Put V before U