Interfaces - Interfaces - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English
The interfaces support:
  • Five input AXI4-Stream interfaces originating from the PL for each ISP Tile, with each supporting single, dual, or quad pixels.
  • Four output AXI4-Stream interfaces (optional) for video output.
  • Two AXI master interfaces connecting to the NoC through NMU, each 128 bits wide.
  • One AXI slave interface receiving data from the NoC through NSU.
  • Provision for clocks, resets, interrupts, and debugging functionalities.