Interfaces and Ports - Interfaces and Ports - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)
Document ID
PG432
Release Date
2025-11-20
Version
2.0 English
Table 1. Input Interfaces
Interface Name Signals Direction Width Description
TILE<0/1/2>_ISP_MIPI_VIDIN<0/1/2/3/4> tile<0/1/2>_if_isp_mipi_vidin<0/1/2/3/4>_tdata I 64 PL to ISP MIPI RX interface
tile<0/1/2>_if_isp_mipi_vidin<0/1/2/3/4>_tdest I 10
tile<0/1/2>_if_isp_mipi_vidin<0/1/2/3/4>_tlast I 1
tile<0/1/2>_if_isp_mipi_vidin<0/1/2/3/4>_tready O 1
tile<0/1/2>_if_isp_mipi_vidin<0/1/2/3/4>_tuser I 96
tile<0/1/2>_if_isp_mipi_vidin<0/1/2/3/4>_tvalid I 1
TILE<0/1/2>_ISP<0/1>_PL_IIC TILE<0/1/2>_ISP<0/1>_PL_IIC_scl_i I 1 IIC interface can be enabled to configure the sensor registers.
TILE<0/1/2>_ISP<0/1>_PL_IIC_scl_o O 1
TILE<0/1/2>_ISP<0/1>_PL_IIC_scl_t O 1
TILE<0/1/2>_ISP<0/1>_PL_IIC_sda_i I 1
TILE<0/1/2>_ISP<0/1>_PL_IIC_sda_o O 1
TILE<0/1/2>_ISP<0/1>_PL_IIC_sda_t O 1
TILE<0/1/2>_ISP<0/1>_PL_GPIO TILE<0/1/2>_ISP<0/1>_PL_GPIO_tri_i I 32 GPIO interface can be enabled to support side band signals associated with sensor configuration.
TILE<0/1/2>_ISP<0/1>_PL_GPIO_tri_o O 32
TILE<0/1/2>_ISP<0/1>_PL_GPIO_tri_t O 32
S_AXI_LITE s_axi_lite_araddr I 16
  • Configures the logi core (LC) registers of ISP/ GPIO/IIC soft IPs in the PL fabric.
  • wstrb is not supported on this interface. It must be 4'b1111 so that always 32-bits are valid.
  • Offset Address of slave address segments of LC registers of ISP, AXI GPIO IP, and AXI IIC IP in PL Fabric is described in the following sections.
s_axi_lite_arready O 1
s_axi_lite_arvalid I 1
s_axi_lite_awaddr O 16
s_axi_lite_awready O 1
s_axi_lite_awvalid I 1
s_axi_lite_bready I 1
s_axi_lite_bvalid O 1
s_axi_lite_bresp O 2
s_axi_lite_rdata O 32
s_axi_lite_rready I 1
s_axi_lite_rvalid O 1
s_axi_lite_rresp O 2
s_axi_lite_wdata I 32
s_axi_lite_wready O 1
s_axi_lite_wvalid I 1
s_axi_lite_wstrb I 4
MIPI_8PPC_VIDIN MIPI_8PPC_VIDIN_tdata I 128 PS to ISP MIPI RX

Interface which supports 8PPC and uses a broadcaster to split the traffic across ISP instances.
MIPI_8PPC_VIDIN_tdest I 10
MIPI_8PPC_VIDIN_tlast I 1
MIPI_8PPC_VIDIN_tready O 1
MIPI_8PPC_VIDIN_tuser I 112
MIPI_8PPC_VIDIN_tvalid I 1
Table 2. Input Interface ISP_NSU
Interface Name Signals Direction Width Description
TILE<0/1/2>_ISP_NSU tile<0/1/2>_if_nsu_isp_intf_araddr I 64 ISP NSU AXI interface is used for ISP register programming.
tile<0/1/2>_if_nsu_isp_intf_arlen I 8
tile<0/1/2>_if_nsu_isp_intf_arsize I 3
tile<0/1/2>_if_nsu_isp_intf_arburst I 2
tile<0/1/2>_if_nsu_isp_intf_arlock I 1
tile<0/1/2>_if_nsu_isp_intf_arcache I 4
tile<0/1/2>_if_nsu_isp_intf_arprot I 3
tile<0/1/2>_if_nsu_isp_intf_arqos I 4
tile<0/1/2>_if_nsu_isp_intf_arvalid I 1
tile<0/1/2>_if_nsu_isp_intf_arready O 1
tile<0/1/2>_if_nsu_isp_intf_arid I 2
tile<0/1/2>_if_nsu_isp_intf_arregion I 4
tile<0/1/2>_if_nsu_isp_intf_aruser I 16
tile<0/1/2>_if_nsu_isp_intf_aruser I 18
tile<0/1/2>_if_nsu_isp_intf_awvalid I 1
tile<0/1/2>_if_nsu_isp_intf_awready O 1
tile<0/1/2>_if_nsu_isp_intf_awid I 2
tile<0/1/2>_if_nsu_isp_intf_awaddr I 64
tile<0/1/2>_if_nsu_isp_intf_awlen I 8
tile<0/1/2>_if_nsu_isp_intf_awsize I 3
tile<0/1/2>_if_nsu_isp_intf_awburst I 2
tile<0/1/2>_if_nsu_isp_intf_awlock I 1
tile<0/1/2>_if_nsu_isp_intf_awcache I 4
tile<0/1/2>_if_nsu_isp_intf_awprot I 3
tile<0/1/2>_if_nsu_isp_intf_awqos I 4
tile<0/1/2>_if_nsu_isp_intf_awregion I 4
tile<0/1/2>_if_nsu_isp_intf_awuser I 16
tile<0/1/2>_if_nsu_isp_intf_awuser I 18
tile<0/1/2>_if_nsu_isp_intf_wvalid I 1
tile<0/1/2>_if_nsu_isp_intf_wready O 1
tile<0/1/2>_if_nsu_isp_intf_wlast I 1
tile<0/1/2>_if_nsu_isp_intf_wid I 6
tile<0/1/2>_if_nsu_isp_intf_wdata I 128
tile<0/1/2>_if_nsu_isp_intf_wstrb I 16
tile<0/1/2>_if_nsu_isp_intf_wuser I 16
tile<0/1/2>_if_nsu_isp_intf_wuser I 17
Table 3. Input Interface ISP_NSU Part 2
Interface Name Signals Direction Width Description
TILE<0/1/2>_ISP_NSU tile<0/1/2>_if_nsu_isp_intf_tdest I 10 ISP NSU AXI interface is used for ISP register programming.
tile<0/1/2>_if_nsu_isp_intf_rvalid O 1
tile<0/1/2>_if_nsu_isp_intf_rready I 1
tile<0/1/2>_if_nsu_isp_intf_rlast O 1
tile<0/1/2>_if_nsu_isp_intf_rid O 2
tile<0/1/2>_if_nsu_isp_intf_rresp O 2
tile<0/1/2>_if_nsu_isp_intf_rdata O 128
tile<0/1/2>_if_nsu_isp_intf_ruser O 16
tile<0/1/2>_if_nsu_isp_intf_ruser O 17
tile<0/1/2>_if_nsu_isp_intf_bvalid O 1
tile<0/1/2>_if_nsu_isp_intf_bready I 1
tile<0/1/2>_if_nsu_isp_intf_bid O 2
tile<0/1/2>_if_nsu_isp_intf_bresp O 2
tile<0/1/2>_if_nsu_isp_intf_buser O 16
Table 4. Output Interfaces
Interface Name Signals Direction Width Description
TILE<0/1/2>_ISP<0/1>_VIDOUT_PO tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tdata O 128 ISP to PL MIPI TX interface
tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tdest O 2
tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tkeep O 6
tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tlast O 1
tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tready I 1
tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tuser O 96
tile<0/1/2>_if_isp<0/1>_1_axis_out_s_axis_tvalid O 1
TILE<0/1/2>_ISP<0/1>_VIDOUT_SO tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tdata O 128 ISP to PL MIPI TX interface
tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tdest O 2
tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tkeep O 6
tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tlast O 1
tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tready I 1
tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tuser O 96
tile<0/1/2>_if_isp<0/1>_2_axis_out_s_axis_tvalid O 1
Table 5. Output Interface ISP_NMU
Interface Name Signals Direction Width Description
TILE<0/1/2>_ISP0_NMU tile<0/1/2>_if_nmu_isp<0/1>_intf_araddr O 64 The processed ISP outputs are written to NOC using AXI write master ports, internally through NOC NMUs.
tile<0/1/2>_if_nmu_isp<0/1>_intf_arburst O 2
tile<0/1/2>_if_nmu_isp<0/1>_intf_arid O 16
tile<0/1/2>_if_nmu_isp<0/1>_intf_arlen O 8
tile<0/1/2>_if_nmu_isp<0/1>_intf_arready I 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_arsize O 3
tile<0/1/2>_if_nmu_isp<0/1>_intf_arvalid O 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_aruser I 18
tile<0/1/2>_if_nmu_isp<0/1>_intf_awaddr O 64
tile<0/1/2>_if_nmu_isp<0/1>_intf_awburst O 2
tile<0/1/2>_if_nmu_isp<0/1>_intf_awid O 16
tile<0/1/2>_if_nmu_isp<0/1>_intf_awlen O 8
tile<0/1/2>_if_nmu_isp<0/1>_intf_awready I 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_awsize O 3
tile<0/1/2>_if_nmu_isp<0/1>_intf_awvalid O 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_awuser O 18
tile<0/1/2>_if_nmu_isp<0/1>_intf_bready O 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_bvalid I 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_bid I 16
Table 6. Output interface ISP_NMU Part 2
Interface Name Signals Direction Width Description
TILE<0/1/2>_ISP0_NMU tile<0/1/2>_if_nmu_isp<0/1>_intf_buser I 16  
tile<0/1/2>_if_nmu_isp<0/1>_intf_rdata I 128
tile<0/1/2>_if_nmu_isp<0/1>_intf_rid I 16
tile<0/1/2>_if_nmu_isp<0/1>_intf_rlast I 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_wdata O 128
tile<0/1/2>_if_nmu_isp<0/1>_intf_wlast O 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_wuser O 18
tile<0/1/2>_if_nmu_isp<0/1>_intf_wid O 16
tile<0/1/2>_if_nmu_isp<0/1>_intf_bresp I 2
tile<0/1/2>_if_nmu_isp<0/1>_intf_rresp I 2
tile<0/1/2>_if_nmu_isp<0/1>_intf_wready I 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_wvalid O 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_awprot O 3
tile<0/1/2>_if_nmu_isp<0/1>_intf_arprot O 3
tile<0/1/2>_if_nmu_isp<0/1>_intf_awcache O 4
tile<0/1/2>_if_nmu_isp<0/1>_intf_arcache O 4
tile<0/1/2>_if_nmu_isp<0/1>_intf_awqos O 4
tile<0/1/2>_if_nmu_isp<0/1>_intf_arqos O 4
tile<0/1/2>_if_nmu_isp<0/1>_intf_wstrb O 16
tile<0/1/2>_if_nmu_isp<0/1>_intf_awregion O 4
tile<0/1/2>_if_nmu_isp<0/1>_intf_arregion O 4
tile<0/1/2>_if_nmu_isp<0/1>_intf_awlock O 1
tile<0/1/2>_if_nmu_isp<0/1>_intf_arlock O 1