Inputs Tab - Inputs Tab - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)
Document ID
PG432
Release Date
2025-11-20
Version
2.0 English
Figure 1. Inputs Tab
Generated by Your Tool
ISP0 Inputs
Core Clock (MHz)
Auto computed to the minimum core clock required based on the following relation. If required, it can be increased up to 800 MHz based on speed grade of the device selected.
Minimum Core Clock calculations
In case of Non-MCM Mode (Number of streaming inputs to ISP<0/1> core is 1)
Minimum core clock = image_width*image_height * frame_rate * 1.2

For example, the resolution 3840x2160 @30 fps:

Minimum Core clock = 3840x2160x30x1.2 = 298.6 MHz.

In case of MCM Mode (Number of streaming inputs to ISP<0/1> core is more than 1)
Minimum Core clock = SUM of PRODUCT (image_width*image_height * frame_rate * 1.2) terms of all the streaming inputs to the ISP<0/1> core.
Example 1
Core with two streaming inputs with the resolutions 3840x2160 @30 fps and 1280 x 720 @30 fps.

Minimum Core clock = (3840 x 2160 x 30 x 1.2) + (1280 x 720 x 30 x 1.2) = 331.776 MHz

Example 2
Core with four streaming inputs with the resolutions 3840x2160 @15 fps, 1920 x 1080 @15 fps, 3840x2160 @15 fps, and 1280 x 720 @15 fps.

Minimum Core clock = (3840 x 2160 x 15 x 1.2) + (1920 x 1080 x 15 x 1.2) + (3840 x 2160 x 15 x 1.2) + (1280 x 720 x 15 x 1.2) = 352.512 MHz

Note: The value of 1.2 accounts for the blanking factor.
Actual Core Clock (MHz)
Generated by the clock generator (DPLL) to achieve the closest possible frequency to the required core clock. This must be greater than or equal to the minimum core clock requirement.

In certain situations where the Actual Core Clock calculated is less the Required Core Clock, a warning displays indicating that you must increase the core clock further to meet your bandwidth requirements.

Common Pixel Format
Only visible and applicable in Basic Mode when the ISP0 IO Type is LIMO and the number of ISP0 Live inputs is greater than 1. Select [RAW8/10/12/16] for the data format input to IBA0/1/2/3*.
Common Pixels per Clock
Only visible and applicable in Basic Mode when the ISP0 IO Type is LIMO and the number of ISP0 Live inputs is greater than 1. Select [1/2/4] for the pixels per clock input to IBA0/1/2/3*.
ISP <0/1> NMU QOS Requirement
Provides the bandwidth values for the NoC IP Wizard to support the selected resolution and frame rate. Refer to Bandwidth Requirement to understand how bandwidth is calculated.
Stream <0/1/2/3*> Configuration
Visible, when the ISP0 IO Type is LILO/LIMO.
Max Horizontal Resolution
Select [720/1280/1920/2048/3840/4096] as the horizontal resolution input to IBA<0/1/2/3*>.
Max Vertical Resolution
Select [480/720/1080/1536/2160/4096] as the vertical resolution input to IBA<0/1/2/3*>.
Pixels Per Clock
Select [1/2/4] pixels to be processed per clock by IBA<0/1/2/3*>.
FPS
Select [10/15/20/25/30/40/45/50/60] for FPS of IBA<0/1/2/3*>.
Pixel Format
Select [RAW8/10/12/16] for the data format input to IBA<0/1/2/3*>. In Basic Mode, this parameter is auto computed based on Common Pixel Format of ISP1 Inputs.
Virtual Channel
Select [0/1/2/3] as the virtual channel ID to be processed by IBA<0/1/2/3*>
ISP1 Inputs
Core Clock (MHz)
Auto computed to the minimum core clock required based on the following relation. If required, it can be increased up to 800 MHz based on speed grade of the device selected.
Minimum Core Clock calculations
In case of Non-MCM Mode (Number of streaming inputs to ISP<0/1> core is 1)
Minimum core clock = image_width*image_height * frame_rate * 1.2

For example, the resolution 3840x2160 @30 fps:

Minimum Core clock = 3840x2160x30x1.2 = 298.6 MHz.

In case of MCM Mode (Number of streaming inputs to ISP<0/1> core is more than 1)
Minimum Core clock = SUM of PRODUCT (image_width*image_height * frame_rate * 1.2) terms of all the streaming inputs to the ISP<0/1> core.
Example 1
Core with two streaming inputs with the resolutions 3840x2160 @30 fps and 1280 x 720 @30 fps.

Minimum Core clock = (3840 x 2160 x 30 x 1.2) + (1280 x 720 x 30 x 1.2) = 331.776 MHz

Note: The value of 1.2 accounts for the blanking factor.
Actual Core Clock (MHz)
Generated by the clock generator (DPLL) to achieve the closest possible frequency to the required core clock. This must be greater than or equal to the minimum core clock requirement.

In certain situations where the Actual Core Clock calculated is less the Required Core Clock, a warning displays indicating that you must increase the core clock further to meet your bandwidth requirements.

Common Pixel Format
Only visible and applicable in Basic Mode when the ISP1 IO Type is LIMO and the number of ISP1 Live inputs is greater than 1. Select [RAW8/10/12/16] for the data format input to IBA3*/4.
Common Pixels per Clock
Only visible and applicable in Basic Mode when the ISP1 IO Type is LIMO and the number of ISP1 Live inputs is greater than 1. Select [1/2/4] for the pixels per clock input to IBA3*/4.
Stream <3*/4> Configuration
Only visible when the ISP1 IO Type is LILO/LIMO.
Max Horizontal Resolution
For the horizontal resolution input to IBA<3*/4>, select from:
  • 720
  • 1280
  • 1920
  • 2048
  • 2840
  • 4096
Max Vertical Resolution
For the vertical resolution input to IBA<3*/4>, select from:
  • 480
  • 720
  • 1080
  • 1536
  • 2160
  • 4096
Pixels Per Clock
Select [1/2/4] pixels to be processed per clock by IBA<3*/4>. In Basic Mode, this parameter is auto computed based on the Common Pixel per Clock of ISP1 Inputs.
FPS
Select [10/15/20/25/30/40/45/50/60] for FPS of IBA<3*/4>.
Pixel Format
Select [RAW8/10/12/16] for the data format input to IBA<3*/4>. In Basic Mode, this parameter is auto computed based on Common Pixel Format of ISP1 Inputs.
Virtual Channel
Select [0/1/2/3] as virtual channel ID to be processed by IBA<3*/4>.