- Open the Vivado Design Suite.
The Vivado IDE Getting Started page contains links to open or create projects and view documentation.
- In the Getting Started page, click Create Project to start the New Project wizard.
- In the Project Name page, name the new project, enter the project location, select Create project subdirectory, and click Next.
- In the Project Type page, specify the type of project to create as RTL Project, deselect Do not specify sources at this time, and click Next.
- In the Add Sources page, click Next.
- In the Add Existing IP (optional) dialog box, click Next.
- In the Add Constraints (optional) dialog box, click Next.
- In the Default Part dialog box, to specify the board for the target device
(VEK385), click Boards, and then click
Next.
- Review the New Project Summary page. Verify that the data displays as
expected, per the preceding steps, and click Finish.
- Click IP Catalog and under Video
Processing, select Versal ISP Subsystem,
and then double-click it.
- You can rename the IP component name. Under the Application Example Design
section, as shown in the following figure, configure the Design Topology
parameter from the following options:
- LILO MIPI Camera to HDMI Display
- LIMO MIPI Camera to HDMI Display
- MIMO DDR to DDR
Based on the mode you select, an appropriate example design generated.
The Generate Output Products dialog box appears.
- Click Generate. (optional) To skip
output products generation, click Skip.
- Under Design Source, right-click the Versal ISP Subsystem
component, and click Open IP Example
Design. Note: Because this step involves the generation of the complete system with multiple subsystems, it takes some time to complete.
- Choose the target project location, then click OK.
Depending on the GUI option you select, the overall system IP integrator block diagram of the VEK385 board-based application example design generates. You can run synthesis, implementation, or generate the device image.
- The following figure shows the system level block design generated when
LILO is selected.
- The following figure shows the system level block design generated when
LIMO is selected.
- The following figure shows the System level block design generated when
MIMO is selected.
- The following figure shows the system level block design generated when
LILO is selected.
- Navigate to .