The following table describes the registers available in the Versal ISP IP with the name, address, and
description of each firmware addressable register within the IP.
Table 1. ISP2 Registers
| Address Offset |
Register Name |
Description |
| 0x00 |
Version control register |
Allows to know the ISP2 IP version. |
| 0x04 |
Soft Reset control register |
Allows to reset each ISP tile separately. |
- The access type and reset value for all the
reserved bits in the registers is read-only with value
0.
- Register accesses must be word aligned, and
there is no support for a write strobe. WSTRB is not used
internally.
- Only the lower 6-bits (5:0) of the read and
write address of the AXI4-Lite
interface are decoded. This means that accessing address
0x00 and 0x40 results in reading the same address of
0x00.
- Reads and writes to addresses outside this
table do not return an error.
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