The MIPI CSI-2 RX Subsystem decodes and processes video data received from the CSI2 camera sensors and delivers it through the AXI4-Stream output interface. The ISP IP processes the AXI4-Stream video data and transfers it to the frame buffer write (FBW) IP as an AXI4-Stream. The Frame Buffer Write IP generates Partial Frame done INTR, which helps to start Frame Buffer Read (FBR) IP earlier than complete frame is available in DDR and displays the processed image on the Display Port (DP). ‘Partial Frame Done INTR’ generated by FBW IP helps improve the latency in the display path.
Figure 1. ISP-DP with Frame Buffer Dataflow Diagram
