When image sensors/cameras cannot make use of the onboard PS IICs, the Versal ISP IP provides options to instantiate PL IIC/GPIO instances as required whose pins are brought out of the IP and can be connected to the IO pins via constraints in the Vivado design.
You can program or access the IIC/GPO instances through the Versal ISP IP S_AXI_LITE interface (Register Space describes the offsets). If these instances need to be controlled by the RPU cores, use the FPD/LPD_AXI_PL interfaces to connect the S_AXI_LITE interface to the PS. Connecting S_AXI_LITE to the PS through the NoC results in RPU’s inability to access these IIC/GPIO resources.