Feature Details - Feature Details - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English

The following section outlines the details of each ISP instance:

  • A maximum pixel rate of 600 megapixel/second (aggregate per ISP instance), which is approximately 4096x3072@40 fps/3840x2160@60 fps.
  • Supports a maximum horizontal or vertical resolution of 4096 pixels.
  • Compatible with standard Bayer input (RGGB, GRBG, GBRG, BGGR), monochrome (CCCC), RYYCy, RCCG, RCCC, and RGB-IR (with 4x4 pattern) sensor types.
  • Supports input pixel depths in linear (8, 10, 12, 14, 16 bits) and compressed (up to 24 bits) formats. Pixel depth does not impact maximum pixel rate.
  • Includes an AXI4-Stream input interface that accepts streaming live data from a Mobile Industry Processor Interface (MIPI) Camera Serial Interface-2 (CSI-2).
  • Accepts Memory-input data from DMA Read functionality.
  • Accepts input test patterns from in-built Test Pattern Generator (TPG).
  • Offers video output formats such as YUV 4:2:0, YUV 4:2:2, Y only, 8, or 10 bits per component, and RGB888 supported through AXI4 -streaming (for Live out) and AXI4 -memory mapped interfaces (for Memory out).
  • Includes dual output capability per ISP instance enabling primary output and secondary output with separate controls. A single ISP instance (at the same time) for different primary and secondary output streams can process one input stream.
  • Includes the capability to process RGB-IR image sensor data and provides RGB data on the primary output and IR data on the secondary output.
  • Includes Functional Safety (FuSa) support that encompasses ASIL-B random and ASIL-D systematic protocols.
  • Supports a 48-bit system address space.
  • Includes Statistics DMA to write image statistics information generated during the frame processing to memory.
  • In Memory Out I/O type, both primary and secondary output DMA supports raster half-DWORD aligned frame buffer format suitable for 10-bit max color depth.
  • Supports digital zoom on both primary and secondary outputs.

The following diagram shows the elements in the ISP processing pipeline.

Figure 1. ISP Core Pipeline Diagram

Each ISP instance includes the following image processing blocks:

  • De-Companding (CPD)
  • RBG & IR Processing (RGBIR)
  • Black Level Compensation (BLS)
  • Lens Shading Correction (LSC)
  • Digital Gain (DGAIN)
  • Auto White Balance Gain (AWB GAIN)
  • Global Tone Mapping (GTM)
  • Wide Dynamic Range Tone Mapping (WDR)
  • Green Equalization (GE)
  • Dead Pixel Correction (DPCC)
  • 2D Noise Reduction (2DNR)
  • De-mosaic (DMSC)
  • Color Correction Matrix (CCM)
  • Gamma Correction (GAMMA)
  • Color Space Conversion (CSC)
  • Edge Enhancement (EE)
  • YUV 422 Conversion (422 CONV)
  • Color Adjustment (CPROC)
  • Crop & Scale (C&R)