Example Design Guidelines - Example Design Guidelines - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English

For expected/proper servicing of the interrupts from the IPs present in the example design, you must connect the interrupts to the corresponding PL to PS interrupt ports on the PSX Wizard in the LPD and FPD domains as shown in the following table.

Table 1. Interrupt Mappings
ISP Subsystem IP Interrupt Port Corresponding PSX Wizard PL to PS Interrupt Port in LPD and FPD Domain
tile0_isp_isr_irq pl_lpd_irq0
tile0_isp_xmpu_interrupt pl_lpd_irq1
tile0_isp0_fusa_irq pl_lpd_irq2
tile0_isp0_isp_irq pl_lpd_irq3
tile0_isp1_fusa_irq pl_lpd_irq4
tile0_isp1_isp_irq pl_lpd_irq5
frmbuf_rd_ss pl_lpd_irq18
frmbuf_wr_ss pl_lpd_irq19
vmix_ss pl_lpd_irq20
axi_timer_hdmi pl_lpd_irq21
v_hdmi_txss1 pl_lpd_irq22
hdmiphy_ss_0/hdmi_gt_controller pl_lpd_irq23
pl_axi_intc (for MIPI interrupts) pl_fpd_irq0
axi_iic_hdmi pl_fpd_irq6
hdmi_rxss pl_fpd_irq7
  1. Th interrupt port mapping is one-to-one. You cannot interchange this port mapping.