Design Guidelines - Design Guidelines - 2.0 English - PG432

Versal AI Edge Series Gen 2 Image Signal Processor (ISP) Product Guide (PG432)

Document ID
PG432
Release Date
2025-11-20
Version
2.0 English

Each ISP tile is configured through its NSU interface (TILE<0/1/2>_ISP_NSU). To ensure proper functionality, you must connect this NSU interface to the LPD_AXI_NOC and PMC_AXI_NOC interfaces from the PS through the NoC.

For the expected/proper servicing of the interrupts from the Versal ISP IP, you must connect the interrupts to the corresponding PL to PS interrupts ports on the PSX Wizard IP in the LPD domain as shown in the following table. The interrupts from the Versal ISP IP route through the PL interface.

Table 1. Interrupt Mappings
ISP Subsystem IP Interrupt Port Corresponding PSX Wizard PL to PS Interrupt Port in LPD Domain
tile0_isp_isr_irq pl_lpd_irq0
tile0_isp_xmpu_interrupt pl_lpd_irq1
tile0_isp0_fusa_irq pl_lpd_irq2
tile0_isp0_isp_irq pl_lpd_irq3
tile0_isp1_fusa_irq pl_lpd_irq4
tile0_isp1_isp_irq pl_lpd_irq5
tile1_isp_isr_irq pl_lpd_irq6
tile1_isp_xmpu_interrupt pl_lpd_irq7
tile1_isp0_fusa_irq pl_lpd_irq8
tile1_isp0_isp_irq pl_lpd_irq9
tile1_isp1_fusa_irq pl_lpd_irq10
tile1_isp1_isp_irq pl_lpd_irq11
tile2_isp_isr_irq pl_lpd_irq12
tile2_isp_xmpu_interrupt pl_lpd_irq13
tile2_isp0_fusa_irq pl_lpd_irq14
tile2_isp0_isp_irq pl_lpd_irq15
tile2_isp1_fusa_irq pl_lpd_irq16
tile2_isp1_isp_irq pl_lpd_irq17
  1. Th interrupt port mapping is one-to-one. You cannot interchange this port mapping.