| Name | Direction | Width | Description |
|---|---|---|---|
| s_axi_lite_aclk | I | 1 | Clock associated with the S_AXI_LITE interface. Frequency Range: 250 to 300 MHz |
| s_axi_lite_rstn | I | 1 | Reset associated with the S_AXI_LITE interface. |
| eol_path<0/1> | O | 1 | Drives the end of line (EOL) on the VCU2 IP, when low latency path<0/1> is enabled. |
| eof_path<0/1> | O | 1 | Drives the end of frame (EOF) on the VCU2 IP, when low latency path<0/1> is enabled. |
| t<0/1/2>_pl_isp_vidin<0/1/2/3/4>_clk | I | 1 | Clock associated with the
TILE<0/1/2>_ISP_MIPI_VIDIN<0/1/2/3/4> interface. Maximum Frequency: 400 MHz |
| tile<0/1/2>_isp_mipi_vidin<0/1/2/3/4>_header_data | I | 32 | Header data (sideband signal) associated with the TILE<0/1/2>_ISP_MIPI_VIDIN<0/1/2/3/4> interface. |
| tile<0/1/2>_isp_mipi_vidin<0/1/2/3/4>_header_valid | I | 1 | Header valid (sideband signal) associated with the TILE<0/1/2>_ISP_MIPI_VIDIN<0/1/2/3/4> interface. |
| tile<0/1/2>_isp_pl_vidout<0/1>_clk | O | 1 | Clock from ISP<0/1> to the PL for TILE<0/1/2> (PO and SO
of ISP<0/1> instance). The PL uses this to loop back for video
streaming interface clocking for TEILE<0/1/2>. Maximum Frequency: 400 MHz |
| tile<0/1/2>_pl_isp_vidout<0/1>_clk | I | 1 | Clock for the Processed Video output stream to the PL for
tile<0/1/2> (PO and SO of ISP<0/1> instance). If loop
back is used, you can connect
TILE<0/1/2>_isp_pl_vidout<0/1>_clk. Maximum Frequency: 400 MHz |
| tile<0/1/2>_nmu<0/1>_axi_clk | O | 1 | Clock associated with the
TILE<0/1/2>_ISP0_NMU interface. Maximum Frequency: 1080 MHz |
| tile<0/1/2>_nsu_axi_clk | O | 1 | Clock associated with the
TILE<0/1/2>_ISP_NSU interface. Maximum Frequency: 360 MHz |
| tile<0/1/2>_isp<0/1>_fusa_irq | O | 1 | ISP<0/1> core instance FUSA interrupt of TILE<0/1/2>. Must connect to LPD interrupts on the Processing System Wizard because it must be severed by the RPU. |
| tile<0/1/2>_isp<0/1>_isp_irq | O | 1 | ISP<0/1> core instance interrupt of TILE<0/1/2>. Must connect to LPD interrupts on the PS Wizard because it must be severed by the RPU. |
| tile<0/1/2>_isp_isr_irq | O | 1 | TILE<0/1/2> ISP ISR interrupt. Must connect to LPD interrupts on the PS Wizard because it must be severed by the RPU. |
| tile<0/1/2>_isp_xmpu_interrupt | O | 1 | TILE<0/1/2> XMPU interrupt. Must connect to LPD interrupts on the PS Wizard because it must be severed by the RPU. |
| tile<0/1/2>_ref_dpll_clk | I | 1 | TILE<0/1/2> reference input clock. Must be driven from the PS
Wizard PL clock output. Frequency Range: As supported by the PL clock from the PS Wizard. |
| tile<0/1/2>_pl_isp_rstn | I | 1 | Resets the DPLL and soft logic modules in the PL fabric. |
| mipi_8ppc_vidin_header_data | I | 32 | Header data (sideband signal) associated with the MIPI_8PPC_VIDIN interface. |
| mipi_8ppc_vidin_header_valid | I | 1 | Header valid (sideband signal) associated with the MIPI_8PPC_VIDIN interface. |
| pl_isp_mipi300M_clk | I | 1 | Clock associated with the MIPI_8PPC_VIDIN interface. You must supply 300 MHz to this port. |
|
|||