The following optional features of the RISC-V External Debug Support, Version 1.0.0-rc3, standard are not supported in the core:
- Register access without halting
- A running hart executing short sequence of instructions
- RISC-V hart halted when a trigger matches an instruction opcode
- Abstract access to non-GPR hart registers
- Register number post-increment (
aarpostincrementbit) - Quick Access abstract command
- Access Memory abstract command
- Hart info (
hartinfo) register - Abstract Command Autoexec (
abstractauto) register - Debug Scratch Register 0 and 1 (
dscratch0,dscratch1) - Trigger Control (
tcontrol) register - Trigger Extra (
textra32) register
Some registers are also implicitly excluded because only a maximum of 32 harts are supported.