The Trace Funnel Control Register is only implemented when external trace is
enabled (C_TRACE_OUTPUT = 1) and when more than one processor is connected to the MDM V
(C_MB_DBG_PORTS > 1).
|
Reserved
|
Empty
|
-
|
Enable
|
Active
|
| 31 |
4 |
3 |
2 |
1 |
0 |
Table 1. Trace Funnel Control Register Bit
Definitions
| Bits |
Name |
Access |
Reset Value |
Description |
| 31:4 |
- |
R |
0 |
Reserved |
| 3 |
trFunnelEmpty |
R |
1 |
Reads 1 when the trace funnel internal buffers are
empty |
| 2 |
- |
R |
0 |
Reserved |
| 1 |
trFunnelEnable |
R/W |
0 |
Trace Funnel enabled. Setting it to 0 flushes any
queued trace data to output. |
| 0 |
trFunnelActive |
R/W |
0 |
Primary activate/reset bit for trace funnel |