Serial Debug Protocol Description - Serial Debug Protocol Description - 1.0 English - PG428

The MDM V has an internal TAP Controller that conforms to the RISC-V DTM. To generate the TAP Controller signals from BSCAN, an internal version of the BSCAN to JTAG Converter LogiCORE IP is used. See BSCAN to JTAG Converter LogiCORE IP Product Guide (PG365) for more information.

The BSCAN to JTAG protocol controls the internal TAP Controller by shifting in data on bscan_ext_tdi. Each transition of the internal TAP Controller requires two bscan_ext_tck cycles, except when in the SHIFT-DR or SHIFT-IR state, where one bscan_ext_tck cycle is required:

• Shift in 00 to set the internal TAP Controller TMS to 0 and perform one internal TCK cycle
• Shift in 01 to set internal TAP Controller TMS to 1 and perform one internal TCK cycle
• To leave the internal TAP Controller SHIFT-DR or SHIFT-IR state, BSCAN must set bscan_ext_tms to 1, which transitions to EXIT1-DR

During accesses to the internal TAP Controller, BSCAN does not need to go to UPDATE-DR but can transition from SHIFT-DR via EXIT1-DR, PAUSE-DR, EXIT2-DR back to SHIFT-DR.

Additionally, the following BSCAN signals must be set according to the protocol:

• bscan_ext_shift must be set in the state SHIFT-DR.
• bscan_ext_update must be set in the state UPDATE-DR.
• bscan_ext_capture must be set in the state CAPTURE-DR.
• bscan_ext_sel must be set to 1 when transfers are directed to MDM RISC-V.
• bscan_ext_drck is not used but must be equal to bscan_ext_tck in the states CAPTURE-DR and SHIFT-DR.
  Figure 1. TAP Controller State Diagram