The Debug_SYS_Rst output can be used to
reset the entire embedded system on the device, including all processors and peripherals.
Normally, it is connected to a proc_sys_reset IP core.
The XSDB command rst can be used to activate the signal.
The Debug bus connecting each individual MicroBlaze V processor handled by the MDM V core, has the Dbg_Rst reset
signal. This signal can be used to only reset an individual processor. The XSDB command
rst -processor can be used to activate the signal for the
selected target processor. The signal is not available when AXI parallel debug is
selected.
The S_AXI_ARESETN input is only used when
Debug register access is enabled, and AXI4-Lite slave
interconnect is used to access the JTAG UART or External Trace components, or when BSCAN is
disabled. Then it is normally set to the same reset as the interconnect.
The M_AXI_ARESETN input is used when System
Bus Memory Access, Embedded Trace Interface is enabled, and AXI4 master interconnect and/or LMB master interfaces are used. Then it must use the same reset
as the interconnect. A corresponding reset for LMB must also be used.