To tailor an MDM V core uniquely for a specific system, certain features can be parametrized in the core design. This allows you to configure a design that only uses the resources required by the system. The features that can be parametrized in MDM designs are shown in the following table.
| Feature / Description | Parameter Name | Allowable Values |
Default Value |
VHDL Type |
|---|---|---|---|---|
| System Parameters | ||||
| Target family | C_FAMILY | See IP Facts | AMD Virtex™ 7 | string |
| Debug Parameters | ||||
| Number of MicroBlaze™ debug ports | C_MB_DBG_PORTS | 0–32 1 | 1 | integer |
| Enable Debug register access from AXI | C_DBG_REG_ACCESS | 0, 1 | 0 | integer |
| Enable AXI Memory Access From Debug | C_DBG_MEM_ACCESS | 0, 1 | 0 | integer |
| UART Parameters | ||||
| Enable JTAG UART | C_USE_UART | 0, 1 | 0 | integer |
| Trace Parameters | ||||
| Select Trace Interface | C_TRACE_OUTPUT | 0 = NONE 4 = EMBEDDED |
0 | integer |
| Advanced Parameters | ||||
| Specifies the JTAG user-defined register used | C_JTAG_CHAIN |
1 = USER1 2 = USER2 3 = USER3 4 = USER4 |
2 | integer |
| Select BSCAN location | C_USE_BSCAN |
0 = INTERNAL 2 = EXTERNAL 3 = NONE 4 = EXTERNAL HIDDEN |
0 | integer |
| Define BSCAN id 2 | C_BSCANID | 0 - 0xFFFFFFFF | 0x0 | integer |
| MicroBlaze Debug connection 2 | C_DEBUG_INTERFACE |
0 = SERIAL 1 = PARALLEL 2 = AXI |
0 | integer |
| Use JTAG BSCAN 2 | C_USE_JTAG_BSCAN | 0, 1 | 1 | integer |
| DTM IDCODE 2 | C_DTM_IDCODE | 0 - 0xFFFFFFFF | 0x93 | integer |
| Use BSCAN switch 2 | C_USE_BSCAN_SWITCH | 0, 1 | 0 | integer |
| Avoid SRL16 and SRL32 FPGA primitives 2 | C_AVOID_PRIMITIVES | 0,1 | 0 | integer |
|
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In addition to the parameters listed in this table, there are also parameters that are inferred for each AXI interface in the tools. Through the design, these inferred parameters control the behavior of the AXI Interconnect. For a complete list of the interconnect settings related to the AXI interface, see the AXI Interconnect LogiCORE IP Product Guide (PG059).