The PIB Sink Control Register is only implemented when external trace is enabled (C_TRACE_OUTPUT = 1).
| Reserved | - | AsyncFreq | - | Calibrate | ClkCenter | Mode | Empty | - | Enable | Active | |||||
| 31 | 16 | 15 | 14 | 12 | 11 | 10 | 9 | 8 | 7 | 4 | 3 | 2 | 1 | 0 | |
| Bits | Name | Access | Reset Value | Description |
|---|---|---|---|---|
| 31:16 | trPibDivider | R | 0x0000 | Timebase selection for the PIB module. Read-only zero. |
| 15 | - | R | 0 | Reserved |
| 14:12 | trPibAsyncFreq | R | 0 | Alignment synchronization packets disabled. Read-only zero. |
| 11:10 | - | R | 00 | Reserved |
| 9 | trPibCalibrate | R/W | 0 | Set this to 1 to generate a repeating calibration pattern |
| 8 | trPibClkCenter | R | 0 |
Adjust TRC_CLK timing to the center of the bit period. Read-only zero. |
| 7:4 | trPibMode | R/W | 0 | Select mode for output pins. Allowed values depend on the selected
trace data width:
|
| 3 | trPibEmpty | R | 1 | Reads 1 when PIB internal buffers are empty |
| 2 | - | R | 0 | Reserved |
| 1 | trPibEnable | R/W | 0 | Enable PIB to generate output |
| 0 | trPibActive | R/W | 0 | Primary activate/reset bit for PIB Sink component |