The MicroBlaze™ Debug Module V supports multiple MicroBlaze V cores, each representing a single RISC-V hardware thread (hart), making it possible to use one MDM V core for multiprocessor systems with up to 32 processors.
In general, when using internal BSCAN it is recommended to use a single MDM V core for all processors. The reason for this is that each additional MDM V core has to use a separate JTAG user-defined register. Because there are only four such registers available, with USER 1 usually reserved for hardware debug, it is a limited resource. Furthermore, the Xilinx System Debugger (XSDB) command line only detects the MDM V core connected to USER 2 by default, and needs to be configured to detect additional MDM V cores. (See Vivado Design Suite User Guide: Programming and Debugging (UG908)) for details.
When using MicroBlaze V and MicroBlaze in the same design it is required to use MDM V with MicroBlaze V and MDM with MicroBlaze. To ensure that both are detected by XSDB it is recommended to either:
- Use internal BSCAN and select user-defined register USER 3 in either MDM or MDM
V.
or
- Use external BSCAN on both MDM V and MDM, and connect them to an AMD Debug Bridge IP (see Debug Bridge LogiCORE IP Product Guide (PG245) for details).
When implementing a MicroBlaze V multiprocessor design in Vivado using Block Automation, all processors are automatically connected to the same MDM V core.