MicroBlaze V Parallel Debug Interface Signals - 1.0 English - PG428

MicroBlaze Debug Module V (MDM V) LogiCORE IP Product Guide (PG428)
Document ID
PG428
Release Date
2025-06-11
Version
1.0 English
Table 1. MicroBlaze V Parallel Debug I/F Signals (n = 0–31)
Signal Name Interface I/O Initial State Description
Dbg_AWADDR_n

MBDEBUG_n

MBDEBUG_AXI_n

 O 0 MicroBlaze debug write address
Dbg_AWVALID_n O 0 MicroBlaze debug write address valid
Dbg_AWREADY_n I - MicroBlaze debug write address ready
Dbg_WDATA_n O 0 MicroBlaze debug write data
Dbg_WVALID_n O 0 MicroBlaze debug write data valid
Dbg_WREADY_n I - MicroBlaze debug write data ready
Dbg_BRESP_n I - MicroBlaze debug write response
Dbg_BVALID_n I - MicroBlaze debug write response valid
Dbg_BREADY_n O 0 MicroBlaze debug write response ready
Dbg_ARADDR_n O 0 MicroBlaze debug read address
Dbg_ARVALID_n O 0 MicroBlaze debug read address valid
Dbg_ARREADY_n I - MicroBlaze debug read address ready
Dbg_RDATA_n I - MicroBlaze debug read data
Dbg_RRESP_n I - MicroBlaze debug read data response
Dbg_RVALID_n I - MicroBlaze debug read data valid
Dbg_RREADY_n O 0 MicroBlaze debug read data ready
  1. The signals are enabled when using:
    • Parallel debug (C_DEBUG_INTERFACE>0)
    • Embedded trace without memory access from debug (C_TRACE_OUTPUT=4 and C_DBG_MEM_ACCESS=0)
    • External trace without debug register access from AXI or memory access from debug (C_TRACE_OUTPUT=1 and C_DBG_REG_ACCESS=0 and C_DBG_MEM_ACCESS=0)