Memory Access
When using the RISC-V System Bus memory access, the AXI4 Master should be connected to access the system
memory accessible by the connected
MicroBlaze™
cores, usually through the processor cache interfaces M_AXI_DC and M_AXI_IC.
Depending on the AXI interconnect topology, this might exclude peripheral I/O
accessed through the processor peripheral interface M_AXI_DP. The LMB Master ports should be connected to access the LMB
local memory of the corresponding processor. This can be done by adding an
additional LMB slave input to the data-side LMB block RAM Interface Controller (see
the
LMB BRAM Interface Controller LogiCORE IP Product
Guide (PG112)).
Trace and Profiling Access
The System Bus can also be connected to the S_AXI interface of the MicroBlaze V cores, giving access to the RISC-V N-Trace (Nexus-based Trace) and Non-intrusive Profiling register space.
As an alternative, the MDM V also allows the System Bus to access Trace and Profiling directly through the normal debug interface, by selecting the Embedded Trace Interface. This option does not require any additional connections between the MDM V and the MicroBlaze V cores.
For detailed information on Trace and Profiling, see MicroBlaze V Processor Reference Guide (UG1629).