Debug Register Space - 1.0 English - PG428

MicroBlaze Debug Module V (MDM V) LogiCORE IP Product Guide (PG428)
Document ID
PG428
Release Date
2025-11-20
Version
1.0 English

The following table lists and describes the MDM V debug registers. These registers are accessible using the debug register access functionality through the AXI4-Lite interface or by the external debugger through JTAG using the internal or external BSCAN. The table also lists all implemented Debug Module, Core, and Trigger registers from the The RISC-V Debug Specification.

When complete illegal instruction exceptions are enabled (MicroBlaze V parameter C_ILL_INSTR_EXCEPTION = 2), attempting to access the unimplemented core registers, dscratch0 and dscratch1, results in an Illegal Instruction exception in debug mode.

Table 1. Register Address Space
Address (hex) Register Name Remark
Debug Module (DM) Registers
04 data0  
10 dmcontrol
  • hartselhi = 0
  • hartsello = 0-31 depending on C_MB_DBG_PORTS

The bits ackunavail, setkeepalive, and clrkeepalive have no effect.
11 dmstatus Read-only bits:
  • ndmresetpending = 0
  • stickyunavail = 0
  • impebreak = 1
  • authenticated = 1
  • authbusy = 0
  • hasresethaltreq = 1
  • confstrptrvalid = 0
  • version = 3

The bits anynonexistent and allnonexistent can only be set if the number of cores (harts) is not 1, 2, 4, 8, 16, or 32.
12 hartinfo Read-only value 0
14 hawindowsel Read-only value 0
15 hawindow Size: 1 - 32 bits depending on C_MB_DBG_PORTS
16 abstractcs Read-only fields:
  • progbufsize = 1
  • datacount = 1

The relaxedpriv field is set to 1 after reset when secure debug is not enabled in the processor; otherwise, it is set to 0. Read-only 0 when secure debug is activated. For detailed information on Secure Debug, see MicroBlaze V Processor Reference Guide (UG1629).
17 command  
18 abstractauto Read-only value 0
19 confstrptr0 Read-only value 0
1d nextdm Read-only value 0
20 progbuf0  
32 dmcs2 Exists when C_USE_CROSS_TRIGGER = 1
38 sbcs Exists when C_DBG_MEM_ACCESS > 0
39 sbaddress0 Exists when C_DBG_MEM_ACCESS > 0
3c sbdata0 Exists when C_DBG_MEM_ACCESS > 0
40 haltsum0  
70 custom0 Exists when C_USE_UART > 0
71 custom1 Exists when C_USE_UART > 0
Core Registers
7b0 dcsr Read-only fields:
  • debugver = 4
  • stopcount = 1
  • stoptime = 1
  • mprven = 0 when MicroBlaze V parameter C_USE_MMU = 0, otherwise 1
  • prv = 3 when MicroBlaze V parameter C_USE_MMU = 0

The field prv and the bit ebreaku are implemented when the MicroBlaze V parameter C_USE_MMU > 0.

The bit ebreaks is implmented when the MicroBlaze V parameter C_USE_MMU > 1.

The bits ebreakm, stepie, cause, and step are always implemented.
7b1 dpc  
Trigger Registers
7a0 tselect 0 - 15: 8 breakpoints, 4 write triggers, 4 read triggers
7a1 tdata1
  • type = 0, 2
  • dmode = 1

The u bit is implemented when the MicroBlaze V parameter C_USE_MMU > 0.
7a2 tdata2 Instruction or data access address
7a4 tinfo Read only value 0005 (hex)