This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.
If you are customizing and generating
the core in the
Vivado IP integrator, see
the
Vivado Design Suite User Guide: Designing
IP Subsystems using IP Integrator (UG994) for
detailed information. IP integrator might auto-compute certain
configuration values when validating or generating the design. To
check whether the values do change, see the description of the
parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl
console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
- Select the IP from the IP catalog.
- Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.
The Customize IP dialog box is shown in the following figure.
- Number of MicroBlaze V debug ports
- Sets the number of ports available to connect to MicroBlaze™ V processors.
- Enable Debug Register Access From AXI
- Enables the functionality to access JTAG Debug registers from AXI and the AXI4-Lite slave interface.
- Enable AXI Memory Access From Debug
- Enables the System Bus functionality to access memory directly from JTAG or parallel debug, using the AXI4 master interface and the LMB master interfaces.
- Enable JTAG UART
- Enables the JTAG UART and the AXI4-Lite slave interface to access the UART registers.
- Select Trace Interface
- Enables RISC-V System Bus Trace and Profiling register space access through the debug ports connected to the MicroBlaze™ V processors.
- Specify the JTAG user-defined register used
- Select JTAG user-defined register. Can be set to USER1, USER2, USER3, or USER4. Should never need to be changed from USER2, unless there is a conflict with another IP core in the system.
- Select BSCAN location
- Selects whether internal or external BSCAN is used, or disables BSCAN. Should normally be set to INTERNAL in an embedded system. Should be set to EXTERNAL or EXTERNAL HIDDEN when debugging with the Xilinx Virtual Cable (XVC) using the Debug Bridge. Can be set to NONE to disable BSCAN completely, when only Debug register access is used and no software debug is required.