The MDM V core provides a programmable cross trigger crossbar to implement the RISC-V Halt Groups, Resume Groups, and External Triggers, described in the RISC-V Debug Specification.
The crossbar allows halt and resume events from each connected processor and the four external trigger inputs to affect each of the connected processors and four external trigger outputs.
When harts are halted because of a group trigger, the Debug Control and Status register cause field is set to 6 (haltreq).
External triggers are treated as bidirectional when configuring a group and are numbered from 0 to 3.
The number of halt groups and resume groups provided depends on the number of
connected processors (harts) defined by C_MB_DBG_PORTS listed in
the following table.
| Harts | Halt Groups | Resume Groups | Harts | Halt Groups | Resume Groups |
|---|---|---|---|---|---|
| 1 | 2 | 2 | 17 | 11 | 11 |
| 2 | 3 | 3 | 18 | 12 | 12 |
| 3 | 4 | 4 | 19 | 12 | 12 |
| 4 | 5 | 5 | 20 | 13 | 13 |
| 5 | 5 | 5 | 21 | 13 | 13 |
| 6 | 6 | 6 | 22 | 14 | 14 |
| 7 | 6 | 6 | 23 | 14 | 14 |
| 8 | 7 | 7 | 24 | 15 | 15 |
| 9 | 7 | 7 | 25 | 15 | 15 |
| 10 | 8 | 8 | 26 | 16 | 16 |
| 11 | 8 | 8 | 27 | 16 | 16 |
| 12 | 9 | 9 | 28 | 17 | 17 |
| 13 | 9 | 9 | 29 | 17 | 17 |
| 14 | 10 | 10 | 30 | 18 | 18 |
| 15 | 10 | 10 | 31 | 18 | 18 |
| 16 | 11 | 11 | 32 | 19 | 19 |
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