The MDM V core block diagram is shown in the following figure.
Feature Summary
- Enables JTAG-based debugging of one or more MicroBlaze™ V processors.
- Instantiates one BSCAN primitive, or allows the use of an external BSCAN. In devices that contain more than one BSCAN primitive, the MDM V core uses the USER2 BSCAN by default.
- External BSCAN also supports connection to the Debug Bridge AMD LogiCORE™
IP, to use the Xilinx Virtual Cable (XVC) for
debugging over non-JTAG interfaces.
In Versal devices the external BSCAN is normally hidden and the Control, Interfaces and Processing System (CIPS) BSCAN is automatically connected by the Vivado Design Suite, which provides a transparent functionality equivalent to other devices. However, if necessary, you can manually connect the CIPS BSCAN to the external BSCAN. For more information on CIPS, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).
- Includes a UART with a configurable slave bus interface, which can be configured for an AXI4-Lite interconnect. The UART TX and RX data transfers over the device JTAG port to and from the System Debugger (XSDB) tool. The UART behaves in a manner similar to the LogiCORE IP AXI (UART) Lite core.
- Provides a configurable AXI4 master port and LMB interfaces for direct access to memory from JTAG or parallel debug, using the RISC-V System Bus function. This allows for a fast program download, as well as transparent memory access when the connected processors are executing.
- Allows software to control debug and observe debug status through the AXI4-Lite slave interface with parallel debug enabled.
- Includes a cross-trigger capability based on RISC-V Halt Groups, Resume Groups, and External Triggers, which enables the routing of events between connected MicroBlaze V processors, as well as an external interface compatible with integrated logic analyzer (ILA) cores and the processing systems in AMD Zynq™ 7000 SoC, AMD Zynq™ UltraScale+™ MPSoC, and Versal devices.
- Includes support for control of RISC-V N-Trace (Nexus-based Trace) components in each connected MicroBlaze V processor through the debug interface, using the RISC-V System Bus function.
- Includes support for external trace interfaces to funnel and transmit MicroBlaze V program trace. Program trace from connected MicroBlaze V processors can be directly output on an external interface using a RISC-V Trace Funnel and Trace PIB Sink.
- Supports MicroBlaze V parallel debug
access, which you can use instead of serial debug to provide faster direct access to
MicroBlaze V debug registers and to improve timing
compared to serial debug.
In general, it is recommended to only use this feature when software debug through JTAG is not required, because otherwise, the MDM V requires additional logic.