The MDM V core block diagram is shown in the following figure.
Feature Summary
- Enables JTAG-based debugging of one or more MicroBlaze™ V processors.
- Instantiates one BSCAN primitive, or allows an external BSCAN to be used. In devices that contain more than one BSCAN primitive, the MDM V core uses the USER2 BSCAN by default.
- External BSCAN also supports connection to the Debug Bridge AMD LogiCORE™
IP, to use the Xilinx Virtual Cable (XVC) for
debugging over non-JTAG interfaces.
In AMD Versal™ devices the external BSCAN is normally hidden and the Control, Interfaces and Processing System (CIPS) BSCAN is automatically connected by the AMD Vivado™ Design Suite, which provides a transparent functionality equivalent to other devices. However, it is possible to manually connect the CIPS BSCAN to the external BSCAN, if necessary. For more information on CIPS, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).
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Includes a UART with a configurable slave bus interface, which can be configured for an AXI4-Lite interconnect. The UART TX and RX data is transferred over the device JTAG port to and from the System Debugger (XSDB) tool. The UART behaves in a manner similar to the LogiCORE IP AXI (UART) Lite core.
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Provides a configurable AXI4 master port and LMB interfaces for direct access to memory from JTAG or parallel debug, using the RISC-V System Bus function. This allows fast program download, as well as transparent memory access when the connected processors are executing.
- Allows software to control debug and observe debug status through the AXI4-Lite slave interface with parallel debug enabled.
- Includes support for control of RISC-V N-Trace (Nexus/based Trace) components in each connected MicroBlaze V processor through the debug interface, using the RISC-V System Bus function.
- Supports MicroBlaze V parallel
debug access, which can be used instead of serial debug to provide faster direct access
to MicroBlaze V debug registers, and to improve
timing compared to serial debug.
In general, it is recommended to only use this feature when software debug through JTAG is not required, because otherwise, the MDM V requires additional logic.