The S_AXI_ACLK input is only used when Debug
register access is enabled, and AXI4-Lite slave
interconnect is
used to access
the JTAG UART or External Trace components, or when BSCAN is disabled. Then
it should normally be set to the same clock as the interconnect.
The M_AXI_ACLK input is used when System Bus
Memory
Access,
Embedded Trace Interface
or External
Trace without debug register access is enabled, and AXI4 master interconnect and/or LMB master interfaces are used. Then it must be
set to the same clock as the interconnect and LMB interfaces. Different clocks for AXI4 and LMB is not supported in this case.
The TRACE_CLK input clock is used when external trace output is selected. This clock could be generated on-chip or be derived from an off-chip source. It can be asynchronous to all other clocks. The nominal clock frequency is 200 MHz. If another clock frequency is used, the parameter C_TRACE_CLK_FREQ_HZ must be manually changed accordingly.
The TRACE_CLK_OUT output clock is a divided by two version of TRACE_CLK, to provide a clock that toggles on both edges of the TRACE_DATA and TRACE_CTL data and control outputs. To create a sample point at a stable point of the outputs, a 90° phase shift is nominally added to the TRACE_CLK_OUT clock. The phase shift can be adjusted manually with the parameter C_TRACE_CLK_OUT_PHASE if necessary.
Apart from the JTAG-based UART, Debug register access, and the trace output, the MDM V core is clocked from the BSCAN when it is enabled, with a clock frequency determined by the JTAG connection.
When programming a System ACE™ device, the MDM V core clock must be at least twice as fast as the System ACE tool controller clock for the ELF file to load correctly.